* [PATCH v4 1/6] dt-bindings: display: imx: Add i.MX8qxp/qm DPU binding
2020-12-10 5:27 [PATCH v4 0/6] drm/imx: Introduce i.MX8qm/qxp DPU DRM Liu Ying
@ 2020-12-10 5:27 ` Liu Ying
2020-12-10 5:27 ` [PATCH v4 2/6] dt-bindings: display: imx: Add i.MX8qxp/qm PRG binding Liu Ying
` (3 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: Liu Ying @ 2020-12-10 5:27 UTC (permalink / raw)
To: linux-arm-kernel, dri-devel, devicetree, linux-kernel
Cc: p.zabel, tzimmermann, airlied, festevam, s.hauer,
maarten.lankhorst, mripard, robh+dt, linux-imx, daniel,
laurentiu.palcu, guido.gunther, shawnguo, kernel
This patch adds bindings for i.MX8qxp/qm Display Processing Unit.
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Liu Ying <victor.liu@nxp.com>
---
Note that this depends on the 'two cell binding' clock patch set which has
already landed in Shawn's i.MX clk/imx git branch. Otherwise, imx8-lpcg.h
won't be found.
v3->v4:
* Improve compatible property by using enum instead of oneOf+const. (Rob)
* Add Rob's R-b tag.
v2->v3:
* No change.
v1->v2:
* Fix yamllint warnings.
* Require bypass0 and bypass1 clocks for both i.MX8qxp and i.MX8qm, as the
display controller subsystem spec does say that they exist.
* Use new dt binding way to add clocks in the example.
* Trivial tweaks for the example.
.../bindings/display/imx/fsl,imx8qxp-dpu.yaml | 416 +++++++++++++++++++++
1 file changed, 416 insertions(+)
create mode 100644 Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dpu.yaml
diff --git a/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dpu.yaml b/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dpu.yaml
new file mode 100644
index 00000000..817c7f3
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dpu.yaml
@@ -0,0 +1,416 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/imx/fsl,imx8qxp-dpu.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale i.MX8qm/qxp Display Processing Unit
+
+maintainers:
+ - Liu Ying <victor.liu@nxp.com>
+
+description: |
+ The Freescale i.MX8qm/qxp Display Processing Unit(DPU) is comprised of two
+ main components that include a blit engine for 2D graphics accelerations
+ and a display controller for display output processing, as well as a command
+ sequencer.
+
+properties:
+ compatible:
+ enum:
+ - fsl,imx8qxp-dpu
+ - fsl,imx8qm-dpu
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ items:
+ - description: |
+ store9 shadow load interrupt(blit engine)
+ - description: |
+ store9 frame complete interrupt(blit engine)
+ - description: |
+ store9 sequence complete interrupt(blit engine)
+ - description: |
+ extdst0 shadow load interrupt
+ (display controller, content stream 0)
+ - description: |
+ extdst0 frame complete interrupt
+ (display controller, content stream 0)
+ - description: |
+ extdst0 sequence complete interrupt
+ (display controller, content stream 0)
+ - description: |
+ extdst4 shadow load interrupt
+ (display controller, safety stream 0)
+ - description: |
+ extdst4 frame complete interrupt
+ (display controller, safety stream 0)
+ - description: |
+ extdst4 sequence complete interrupt
+ (display controller, safety stream 0)
+ - description: |
+ extdst1 shadow load interrupt
+ (display controller, content stream 1)
+ - description: |
+ extdst1 frame complete interrupt
+ (display controller, content stream 1)
+ - description: |
+ extdst1 sequence complete interrupt
+ (display controller, content stream 1)
+ - description: |
+ extdst5 shadow load interrupt
+ (display controller, safety stream 1)
+ - description: |
+ extdst5 frame complete interrupt
+ (display controller, safety stream 1)
+ - description: |
+ extdst5 sequence complete interrupt
+ (display controller, safety stream 1)
+ - description: |
+ disengcfg0 shadow load interrupt
+ (display controller, display stream 0)
+ - description: |
+ disengcfg0 frame complete interrupt
+ (display controller, display stream 0)
+ - description: |
+ disengcfg0 sequence complete interrupt
+ (display controller, display stream 0)
+ - description: |
+ framegen0 programmable interrupt0
+ (display controller, display stream 0)
+ - description: |
+ framegen0 programmable interrupt1
+ (display controller, display stream 0)
+ - description: |
+ framegen0 programmable interrupt2
+ (display controller, display stream 0)
+ - description: |
+ framegen0 programmable interrupt3
+ (display controller, display stream 0)
+ - description: |
+ signature0 shadow load interrupt
+ (display controller, display stream 0)
+ - description: |
+ signature0 measurement valid interrupt
+ (display controller, display stream 0)
+ - description: |
+ signature0 error condition interrupt
+ (display controller, display stream 0)
+ - description: |
+ disengcfg1 shadow load interrupt
+ (display controller, display stream 1)
+ - description: |
+ disengcfg1 frame complete interrupt
+ (display controller, display stream 1)
+ - description: |
+ disengcfg1 sequence complete interrupt
+ (display controller, display stream 1)
+ - description: |
+ framegen1 programmable interrupt0
+ (display controller, display stream 1)
+ - description: |
+ framegen1 programmable interrupt1
+ (display controller, display stream 1)
+ - description: |
+ framegen1 programmable interrupt2
+ (display controller, display stream 1)
+ - description: |
+ framegen1 programmable interrupt3
+ (display controller, display stream 1)
+ - description: |
+ signature1 shadow load interrupt
+ (display controller, display stream 1)
+ - description: |
+ signature1 measurement valid interrupt
+ (display controller, display stream 1)
+ - description: |
+ signature1 error condition interrupt
+ (display controller, display stream 1)
+ - description: |
+ command sequencer error condition interrupt(command sequencer)
+ - description: |
+ common control software interrupt0(common control)
+ - description: |
+ common control software interrupt1(common control)
+ - description: |
+ common control software interrupt2(common control)
+ - description: |
+ common control software interrupt3(common control)
+ - description: |
+ framegen0 sychronization status activated interrupt
+ (display controller, safety stream 0)
+ - description: |
+ framegen0 sychronization status deactivated interrupt
+ (display controller, safety stream 0)
+ - description: |
+ framegen0 sychronization status activated interrupt
+ (display controller, content stream 0)
+ - description: |
+ framegen0 sychronization status deactivated interrupt
+ (display controller, content stream 0)
+ - description: |
+ framegen1 sychronization status activated interrupt
+ (display controller, safety stream 1)
+ - description: |
+ framegen1 sychronization status deactivated interrupt
+ (display controller, safety stream 1)
+ - description: |
+ framegen1 sychronization status activated interrupt
+ (display controller, content stream 1)
+ - description: |
+ framegen1 sychronization status deactivated interrupt
+ (display controller, content stream 1)
+
+ interrupt-names:
+ items:
+ - const: store9_shdload
+ - const: store9_framecomplete
+ - const: store9_seqcomplete
+ - const: extdst0_shdload
+ - const: extdst0_framecomplete
+ - const: extdst0_seqcomplete
+ - const: extdst4_shdload
+ - const: extdst4_framecomplete
+ - const: extdst4_seqcomplete
+ - const: extdst1_shdload
+ - const: extdst1_framecomplete
+ - const: extdst1_seqcomplete
+ - const: extdst5_shdload
+ - const: extdst5_framecomplete
+ - const: extdst5_seqcomplete
+ - const: disengcfg_shdload0
+ - const: disengcfg_framecomplete0
+ - const: disengcfg_seqcomplete0
+ - const: framegen0_int0
+ - const: framegen0_int1
+ - const: framegen0_int2
+ - const: framegen0_int3
+ - const: sig0_shdload
+ - const: sig0_valid
+ - const: sig0_error
+ - const: disengcfg_shdload1
+ - const: disengcfg_framecomplete1
+ - const: disengcfg_seqcomplete1
+ - const: framegen1_int0
+ - const: framegen1_int1
+ - const: framegen1_int2
+ - const: framegen1_int3
+ - const: sig1_shdload
+ - const: sig1_valid
+ - const: sig1_error
+ - const: cmdseq_error
+ - const: comctrl_sw0
+ - const: comctrl_sw1
+ - const: comctrl_sw2
+ - const: comctrl_sw3
+ - const: framegen0_primsync_on
+ - const: framegen0_primsync_off
+ - const: framegen0_secsync_on
+ - const: framegen0_secsync_off
+ - const: framegen1_primsync_on
+ - const: framegen1_primsync_off
+ - const: framegen1_secsync_on
+ - const: framegen1_secsync_off
+
+ clocks:
+ maxItems: 8
+
+ clock-names:
+ items:
+ - const: axi
+ - const: cfg
+ - const: pll0
+ - const: pll1
+ - const: bypass0
+ - const: bypass1
+ - const: disp0
+ - const: disp1
+
+ power-domains:
+ items:
+ - description: DC power-domain
+ - description: PLL0 power-domain
+ - description: PLL1 power-domain
+
+ power-domain-names:
+ items:
+ - const: dc
+ - const: pll0
+ - const: pll1
+
+ fsl,dpr-channels:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description: |
+ List of phandle which points to DPR channels associated with
+ this DPU instance.
+
+ ports:
+ type: object
+ description: |
+ A node containing DPU output port nodes with endpoint definitions
+ as documented in
+ Documentation/devicetree/bindings/media/video-interfaces.txt
+ Documentation/devicetree/bindings/graph.txt
+
+ properties:
+ '#address-cells':
+ const: 1
+
+ '#size-cells':
+ const: 0
+
+ port@0:
+ type: object
+ description: The DPU output port node from display stream0.
+
+ properties:
+ reg:
+ const: 0
+
+ required:
+ - reg
+
+ port@1:
+ type: object
+ description: The DPU output port node from display stream1.
+
+ properties:
+ reg:
+ const: 1
+
+ required:
+ - reg
+
+ required:
+ - "#address-cells"
+ - "#size-cells"
+ - port@0
+ - port@1
+
+ additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - interrupt-names
+ - clocks
+ - clock-names
+ - power-domains
+ - power-domain-names
+ - fsl,dpr-channels
+ - ports
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/imx8-lpcg.h>
+ #include <dt-bindings/firmware/imx/rsrc.h>
+ dpu@56180000 {
+ compatible = "fsl,imx8qxp-dpu";
+ reg = <0x56180000 0x40000>;
+ interrupt-parent = <&dc0_irqsteer>;
+ interrupts = <448>, <449>, <450>, <64>,
+ <65>, <66>, <67>, <68>,
+ <69>, <70>, <193>, <194>,
+ <195>, <196>, <197>, <72>,
+ <73>, <74>, <75>, <76>,
+ <77>, <78>, <79>, <80>,
+ <81>, <199>, <200>, <201>,
+ <202>, <203>, <204>, <205>,
+ <206>, <207>, <208>, <0>,
+ <1>, <2>, <3>, <4>,
+ <82>, <83>, <84>, <85>,
+ <209>, <210>, <211>, <212>;
+ interrupt-names = "store9_shdload",
+ "store9_framecomplete",
+ "store9_seqcomplete",
+ "extdst0_shdload",
+ "extdst0_framecomplete",
+ "extdst0_seqcomplete",
+ "extdst4_shdload",
+ "extdst4_framecomplete",
+ "extdst4_seqcomplete",
+ "extdst1_shdload",
+ "extdst1_framecomplete",
+ "extdst1_seqcomplete",
+ "extdst5_shdload",
+ "extdst5_framecomplete",
+ "extdst5_seqcomplete",
+ "disengcfg_shdload0",
+ "disengcfg_framecomplete0",
+ "disengcfg_seqcomplete0",
+ "framegen0_int0",
+ "framegen0_int1",
+ "framegen0_int2",
+ "framegen0_int3",
+ "sig0_shdload",
+ "sig0_valid",
+ "sig0_error",
+ "disengcfg_shdload1",
+ "disengcfg_framecomplete1",
+ "disengcfg_seqcomplete1",
+ "framegen1_int0",
+ "framegen1_int1",
+ "framegen1_int2",
+ "framegen1_int3",
+ "sig1_shdload",
+ "sig1_valid",
+ "sig1_error",
+ "cmdseq_error",
+ "comctrl_sw0",
+ "comctrl_sw1",
+ "comctrl_sw2",
+ "comctrl_sw3",
+ "framegen0_primsync_on",
+ "framegen0_primsync_off",
+ "framegen0_secsync_on",
+ "framegen0_secsync_off",
+ "framegen1_primsync_on",
+ "framegen1_primsync_off",
+ "framegen1_secsync_on",
+ "framegen1_secsync_off";
+ clocks = <&dc0_dpu_lpcg IMX_LPCG_CLK_5>,
+ <&dc0_dpu_lpcg IMX_LPCG_CLK_4>,
+ <&clk IMX_SC_R_DC_0_PLL_0 IMX_SC_PM_CLK_PLL>,
+ <&clk IMX_SC_R_DC_0_PLL_1 IMX_SC_PM_CLK_PLL>,
+ <&clk IMX_SC_R_DC_0_VIDEO0 IMX_SC_PM_CLK_BYPASS>,
+ <&clk IMX_SC_R_DC_0_VIDEO1 IMX_SC_PM_CLK_BYPASS>,
+ <&dc0_disp_lpcg IMX_LPCG_CLK_0>,
+ <&dc0_disp_lpcg IMX_LPCG_CLK_1>;
+ clock-names = "axi", "cfg",
+ "pll0", "pll1", "bypass0", "bypass1",
+ "disp0", "disp1";
+ power-domains = <&pd IMX_SC_R_DC_0>,
+ <&pd IMX_SC_R_DC_0_PLL_0>,
+ <&pd IMX_SC_R_DC_0_PLL_1>;
+ power-domain-names = "dc", "pll0", "pll1";
+ fsl,dpr-channels = <&dc0_dpr1_channel1>,
+ <&dc0_dpr1_channel2>,
+ <&dc0_dpr1_channel3>,
+ <&dc0_dpr2_channel1>,
+ <&dc0_dpr2_channel2>,
+ <&dc0_dpr2_channel3>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dpu0_disp0_pixel_combiner0_ch0: endpoint {
+ remote-endpoint = <&pixel_combiner0_ch0_dpu0_disp0>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dpu0_disp1_pixel_combiner0_ch1: endpoint {
+ remote-endpoint = <&pixel_combiner0_ch1_dpu0_disp1>;
+ };
+ };
+ };
+ };
--
2.7.4
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^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH v4 3/6] dt-bindings: display: imx: Add i.MX8qxp/qm DPR channel binding
2020-12-10 5:27 [PATCH v4 0/6] drm/imx: Introduce i.MX8qm/qxp DPU DRM Liu Ying
2020-12-10 5:27 ` [PATCH v4 1/6] dt-bindings: display: imx: Add i.MX8qxp/qm DPU binding Liu Ying
2020-12-10 5:27 ` [PATCH v4 2/6] dt-bindings: display: imx: Add i.MX8qxp/qm PRG binding Liu Ying
@ 2020-12-10 5:27 ` Liu Ying
2020-12-10 5:27 ` [PATCH v4 4/6] drm/atomic: Avoid unused-but-set-variable warning on for_each_old_plane_in_state Liu Ying
2020-12-10 5:27 ` [PATCH v4 6/6] MAINTAINERS: add maintainer for i.MX8qxp DPU DRM driver Liu Ying
4 siblings, 0 replies; 6+ messages in thread
From: Liu Ying @ 2020-12-10 5:27 UTC (permalink / raw)
To: linux-arm-kernel, dri-devel, devicetree, linux-kernel
Cc: p.zabel, tzimmermann, airlied, festevam, s.hauer,
maarten.lankhorst, mripard, robh+dt, linux-imx, daniel,
laurentiu.palcu, guido.gunther, shawnguo, kernel
This patch adds bindings for i.MX8qxp/qm Display Prefetch Resolve Channel.
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Liu Ying <victor.liu@nxp.com>
---
Note that this depends on the 'two cell binding' clock patch set which has
already landed in Shawn's i.MX clk/imx git branch. Otherwise, imx8-lpcg.h
won't be found.
v3->v4:
* Improve compatible property by using enum instead of oneOf+const. (Rob)
* Add Rob's R-b tag.
v2->v3:
* No change.
v1->v2:
* Use new dt binding way to add clocks in the example.
.../bindings/display/imx/fsl,imx8qxp-dprc.yaml | 87 ++++++++++++++++++++++
1 file changed, 87 insertions(+)
create mode 100644 Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dprc.yaml
diff --git a/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dprc.yaml b/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dprc.yaml
new file mode 100644
index 00000000..9e05c83
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dprc.yaml
@@ -0,0 +1,87 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/imx/fsl,imx8qxp-dprc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale i.MX8qm/qxp Display Prefetch Resolve Channel
+
+maintainers:
+ - Liu Ying <victor.liu@nxp.com>
+
+description: |
+ The i.MX8qm/qxp Display Prefetch Resolve Channel(DPRC) is an engine which
+ fetches display data before the display pipeline needs the data to drive
+ pixels in the active display region. This data is transformed, or resolved,
+ from a variety of tiled buffer formats into linear format, if needed.
+ The DPR works with a double bank memory structure. This memory structure is
+ implemented in the Resolve Tile Memory(RTRAM) and the banks are referred to
+ as A and B. Each bank is either 4 or 8 lines high depending on the source
+ frame buffer format.
+
+properties:
+ compatible:
+ enum:
+ - fsl,imx8qxp-dpr-channel
+ - fsl,imx8qm-dpr-channel
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: apb clock
+ - description: b clock
+ - description: rtram clock
+
+ clock-names:
+ items:
+ - const: apb
+ - const: b
+ - const: rtram
+
+ fsl,sc-resource:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: The SCU resource ID associated with this DPRC instance.
+
+ fsl,prgs:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description: |
+ List of phandle which points to Prefetch Resolve Gaskets(PRGs)
+ associated with this DPRC instance.
+
+ power-domains:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+ - fsl,sc-resource
+ - fsl,prgs
+ - power-domains
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/imx8-lpcg.h>
+ #include <dt-bindings/firmware/imx/rsrc.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ dpr-channel@56100000 {
+ compatible = "fsl,imx8qxp-dpr-channel";
+ reg = <0x56100000 0x10000>;
+ interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&dc0_dpr1_lpcg IMX_LPCG_CLK_4>,
+ <&dc0_dpr1_lpcg IMX_LPCG_CLK_5>,
+ <&dc0_rtram1_lpcg IMX_LPCG_CLK_0>;
+ clock-names = "apb", "b", "rtram";
+ fsl,sc-resource = <IMX_SC_R_DC_0_VIDEO0>;
+ fsl,prgs = <&dc0_prg4>, <&dc0_prg5>;
+ power-domains = <&pd IMX_SC_R_DC_0>;
+ };
--
2.7.4
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^ permalink raw reply related [flat|nested] 6+ messages in thread