From: heiko@sntech.de (Heiko Stübner)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v5 1/4] clk: rockchip: fix big.LITTLE cores alternate reparent failed
Date: Sun, 27 Mar 2016 23:26:52 +0200 [thread overview]
Message-ID: <1608479.lxyeMomFsd@diego> (raw)
In-Reply-To: <1458974276-10325-2-git-send-email-zhengxing@rock-chips.com>
Am Samstag, 26. M?rz 2016, 14:37:53 schrieb Xing Zheng:
> On the RK3399, the order of the core's parents are LPLL/BPLL/DPLL/GPLL,
> there is incorrect to select bit_0 and bit_1 as the main and alternate
> parents for LPLL/BPLL. They should be configurable.
>
> Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
I've folded this fix into the original patch [0]
Thanks
Heiko
[0] https://git.kernel.org/cgit/linux/kernel/git/mmind/linux-rockchip.git/commit/?h=v4.7-clk/next&id=268aebaa2410152bf91ea1ede6b284ff8138822d
next prev parent reply other threads:[~2016-03-27 21:26 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-03-26 6:37 [PATCH v5 0/4] Add more clock compatible features and support the RK3399 clock Xing Zheng
2016-03-26 6:37 ` [PATCH v5 1/4] clk: rockchip: fix big.LITTLE cores alternate reparent failed Xing Zheng
2016-03-26 8:26 ` kbuild test robot
2016-03-27 21:26 ` Heiko Stübner [this message]
2016-03-26 6:37 ` [PATCH v5 2/4] dt-bindings: add bindings for rk3399 clock controller Xing Zheng
2016-03-27 23:52 ` Heiko Stübner
2016-03-28 0:07 ` Heiko Stuebner
2016-03-28 3:24 ` Xing Zheng
2016-03-28 2:51 ` Xing Zheng
2016-03-26 6:37 ` [PATCH v5 4/4] clk: rockchip: add clock controller for the RK3399 Xing Zheng
2016-03-26 8:41 ` kbuild test robot
2016-03-28 0:13 ` Heiko Stuebner
2016-03-28 6:11 ` Xing Zheng
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