From: CK Hu <ck.hu@mediatek.com>
To: Hsin-Yi Wang <hsinyi@chromium.org>
Cc: Mark Rutland <mark.rutland@arm.com>,
devicetree@vger.kernel.org,
Philipp Zabel <p.zabel@pengutronix.de>,
David Airlie <airlied@linux.ie>,
linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org,
Yongqiang Niu <yongqiang.niu@mediatek.com>,
linux-mediatek@lists.infradead.org,
Daniel Vetter <daniel@ffwll.ch>,
Matthias Brugger <matthias.bgg@gmail.com>,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v4 4/8] drm/mediatek: enable OVL_LAYER_SMI_ID_EN for multi-layer usecase
Date: Fri, 29 Jan 2021 16:21:40 +0800 [thread overview]
Message-ID: <1611908500.31184.6.camel@mtksdaap41> (raw)
In-Reply-To: <20210129073436.2429834-5-hsinyi@chromium.org>
Hi, Hsin-Yi:
On Fri, 2021-01-29 at 15:34 +0800, Hsin-Yi Wang wrote:
> From: Yongqiang Niu <yongqiang.niu@mediatek.com>
>
> enable OVL_LAYER_SMI_ID_EN for multi-layer usecase, without this patch,
> ovl will hang up when more than 1 layer enabled.
Reviewed-by: CK Hu <ck.hu@mediatek.com>
>
> Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org>
> ---
> drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 17 +++++++++++++++++
> 1 file changed, 17 insertions(+)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> index da7e38a28759b..961f87f8d4d15 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> @@ -24,6 +24,7 @@
> #define DISP_REG_OVL_RST 0x0014
> #define DISP_REG_OVL_ROI_SIZE 0x0020
> #define DISP_REG_OVL_DATAPATH_CON 0x0024
> +#define OVL_LAYER_SMI_ID_EN BIT(0)
> #define OVL_BGCLR_SEL_IN BIT(2)
> #define DISP_REG_OVL_ROI_BGCLR 0x0028
> #define DISP_REG_OVL_SRC_CON 0x002c
> @@ -62,6 +63,7 @@ struct mtk_disp_ovl_data {
> unsigned int gmc_bits;
> unsigned int layer_nr;
> bool fmt_rgb565_is_0;
> + bool smi_id_en;
> };
>
> /**
> @@ -134,6 +136,13 @@ void mtk_ovl_start(struct device *dev)
> {
> struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);
>
> + if (ovl->data->smi_id_en) {
> + unsigned int reg;
> +
> + reg = readl(ovl->regs + DISP_REG_OVL_DATAPATH_CON);
> + reg = reg | OVL_LAYER_SMI_ID_EN;
> + writel_relaxed(reg, ovl->regs + DISP_REG_OVL_DATAPATH_CON);
> + }
> writel_relaxed(0x1, ovl->regs + DISP_REG_OVL_EN);
> }
>
> @@ -142,6 +151,14 @@ void mtk_ovl_stop(struct device *dev)
> struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);
>
> writel_relaxed(0x0, ovl->regs + DISP_REG_OVL_EN);
> + if (ovl->data->smi_id_en) {
> + unsigned int reg;
> +
> + reg = readl(ovl->regs + DISP_REG_OVL_DATAPATH_CON);
> + reg = reg & ~OVL_LAYER_SMI_ID_EN;
> + writel_relaxed(reg, ovl->regs + DISP_REG_OVL_DATAPATH_CON);
> + }
> +
> }
>
> void mtk_ovl_config(struct device *dev, unsigned int w,
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next prev parent reply other threads:[~2021-01-29 8:23 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-01-29 7:34 [PATCH v4 0/8] drm/mediatek: add support for mediatek SOC MT8192 Hsin-Yi Wang
2021-01-29 7:34 ` [PATCH v4 1/8] drm/mediatek: add component OVL_2L2 Hsin-Yi Wang
2021-01-29 7:34 ` [PATCH v4 2/8] drm/mediatek: add component POSTMASK Hsin-Yi Wang
2021-01-29 8:18 ` CK Hu
2021-01-29 8:32 ` Yongqiang Niu
2021-01-29 8:35 ` CK Hu, CK Hu, CK Hu
2021-01-29 8:49 ` Yongqiang Niu
2021-01-29 8:51 ` Hsin-Yi Wang
2021-01-29 7:34 ` [PATCH v4 3/8] drm/mediatek: add component RDMA4 Hsin-Yi Wang
2021-01-29 7:34 ` [PATCH v4 4/8] drm/mediatek: enable OVL_LAYER_SMI_ID_EN for multi-layer usecase Hsin-Yi Wang
2021-01-29 8:21 ` CK Hu [this message]
2021-01-31 3:56 ` Chun-Kuang Hu
2021-01-29 7:34 ` [PATCH v4 5/8] drm/mediatek: separate ccorr module Hsin-Yi Wang
2021-01-31 4:07 ` Chun-Kuang Hu
2021-01-29 7:34 ` [PATCH v4 6/8] drm/mediatek: add matrix bits private data for ccorr Hsin-Yi Wang
2021-01-29 8:40 ` CK Hu
2021-01-29 8:59 ` Yongqiang Niu
2021-01-29 7:34 ` [PATCH v4 7/8] soc: mediatek: add mtk mutex support for MT8192 Hsin-Yi Wang
2021-01-29 8:42 ` CK Hu
2021-01-29 7:34 ` [PATCH v4 8/8] drm/mediatek: add support for mediatek SOC MT8192 Hsin-Yi Wang
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