From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.0 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4EEE7C433E0 for ; Fri, 29 Jan 2021 14:29:40 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C1FFC64DF1 for ; Fri, 29 Jan 2021 14:29:39 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org C1FFC64DF1 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=xilinx.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-ID:Date: Subject:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=pqDWoHjHUFWl/GzeCvPtgQJgDu0HzjQ5gW4aee32MJM=; b=ShYu+sTvUUA8slmZlKHRr8hNd lIav6FeLKFolsDZuAb8mkn4iRMWnhjTcK3IfP3Uwk/oSLICvh6lIK/t0T17Mqt2quG1Jm+/Jw+FP3 u5fOjaba0SBJOj6YDdWtG3AC5z2GPuyP6ZfGU3rUOvRwR1j8KseSc/SoCOFyu8ghzkr5i6UOTyvW6 e+PBUlqtsDvWA883uz1p1uP5ErW5M9h9cGIAPhdDtM0mFVfp1dfJry1LZ38LVUrsEhzYfkMLfabHR 6vMYwX8XfyIzf9uUtiYLSPfLvOPYeZ/a9BV4TTfouDRqqKz6r8mZdIqQVGvlonrLvsbnUqVbmv9QU WdpZdoI8Q==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1l5Ukz-00074d-L2; Fri, 29 Jan 2021 14:28:17 +0000 Received: from mail-dm6nam12on2073.outbound.protection.outlook.com ([40.107.243.73] helo=NAM12-DM6-obe.outbound.protection.outlook.com) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1l5Ukw-00072u-6k for linux-arm-kernel@lists.infradead.org; Fri, 29 Jan 2021 14:28:15 +0000 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=acRvMQGtk8nrm9VKAtTVQrDwNcWwbXZKYVILPdHJIRSNG5zcMRzKeairIN4ez2Tow+Eb7833ocCkcovIPdKP2wtw+A1tgAp6n7r7pVlARxmDvcKyNvWs8diDkgU5emCVtVE3TOpK4YDieYZHvcG+gWr+fEdWFMW7sTz7wRX5j5Mzk1uI9qFJtglEaLUbWKb7SHMjy+19M4fetNlSvDQhB4k/MiLa8iMpPGtVSnhNIHcwMwjzLrd7rxWI6DxN0snY6aX5K518UpIU3C1vqN/VUpS3sTi3RtjNYox/83+HU/5eZKu4OjKGODrm0qpTuE872/3c8QDUC6jNbvY++gY1JA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=5kiYTkQ6CNF4A1svU0qtvfJg7LCz3Io0jWVj8M+5SaY=; b=oTTxVMkEnZyBio4fYwRDQNRoxEsKPRTI9j94v3TdYowdk9tXMSZ+cZNzjPCjx2QyktDiFQ8C0LYG4ADU0xXTqw9Man1MZr4cUAM33tjKxRN4t8POdTtxfRAljohuO1ewp+QcA5S0vM1AglvqY++neqSWD5mNEBdrj3aiTh7Wk2W+CXjIf8CZdFxD0pxl+ki9p640EQYXn9o2RKMp6m1FpYM9l937HLoUVZcqybHEbeRpfdnCc6xbkwszZRGH3S5McX5UN74LCSMEAfMidqN8eYkoBRFriGl++x0m5pDfMYPFXSrk2cH6hWVnImC81P1AXV+6rUvZ9ub+spw2bUcF9g== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 149.199.62.198) smtp.rcpttodomain=linaro.org smtp.mailfrom=xilinx.com; dmarc=bestguesspass action=none header.from=xilinx.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=xilinx.onmicrosoft.com; s=selector2-xilinx-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=5kiYTkQ6CNF4A1svU0qtvfJg7LCz3Io0jWVj8M+5SaY=; b=rTBGcImTMuhHIeKoziZfqxscG+sjmndhyrHW9LtNR5V+8MNH8/AKj+DC+KWjZQQ8UTRLou4NrN3lQLfqfTc0JAuNTV02OZiU+Ta/Vz2koYfy3rBidPJwk0Glt0I4AALCHKfpcWAyN+1RltsQsmSFizm7Io4qSEd2/hcCst7G2NE= Received: from CY4PR22CA0052.namprd22.prod.outlook.com (2603:10b6:903:ae::14) by SN6PR02MB4606.namprd02.prod.outlook.com (2603:10b6:805:b0::28) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3784.12; Fri, 29 Jan 2021 14:28:05 +0000 Received: from CY1NAM02FT042.eop-nam02.prod.protection.outlook.com (2603:10b6:903:ae:cafe::da) by CY4PR22CA0052.outlook.office365.com (2603:10b6:903:ae::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3805.16 via Frontend Transport; Fri, 29 Jan 2021 14:28:05 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 149.199.62.198) smtp.mailfrom=xilinx.com; linaro.org; dkim=none (message not signed) header.d=none;linaro.org; dmarc=bestguesspass action=none header.from=xilinx.com; Received-SPF: Pass (protection.outlook.com: domain of xilinx.com designates 149.199.62.198 as permitted sender) receiver=protection.outlook.com; client-ip=149.199.62.198; helo=xsj-pvapexch01.xlnx.xilinx.com; Received: from xsj-pvapexch01.xlnx.xilinx.com (149.199.62.198) by CY1NAM02FT042.mail.protection.outlook.com (10.152.75.136) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.3784.12 via Frontend Transport; Fri, 29 Jan 2021 14:28:05 +0000 Received: from xsj-pvapexch02.xlnx.xilinx.com (172.19.86.41) by xsj-pvapexch01.xlnx.xilinx.com (172.19.86.40) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1913.5; Fri, 29 Jan 2021 06:27:05 -0800 Received: from smtp.xilinx.com (172.19.127.95) by xsj-pvapexch02.xlnx.xilinx.com (172.19.86.41) with Microsoft SMTP Server id 15.1.1913.5 via Frontend Transport; Fri, 29 Jan 2021 06:27:05 -0800 Received: from [10.140.6.6] (port=56658 helo=xhdappanad40.xilinx.com) by smtp.xilinx.com with esmtp (Exim 4.90) (envelope-from ) id 1l5Ujo-00005L-M5; Fri, 29 Jan 2021 06:27:05 -0800 From: Srinivas Neeli To: , , , , , , Subject: [PATCH V5 2/5] gpio: gpio-xilinx: Reduce spinlock array to array Date: Fri, 29 Jan 2021 19:56:47 +0530 Message-ID: <1611930410-25747-3-git-send-email-srinivas.neeli@xilinx.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1611930410-25747-1-git-send-email-srinivas.neeli@xilinx.com> References: <1611930410-25747-1-git-send-email-srinivas.neeli@xilinx.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 2b52d6e3-5916-4a09-03c5-08d8c4621780 X-MS-TrafficTypeDiagnostic: SN6PR02MB4606: X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:4941; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: gKJWEtFYPcGLa8fZDJYCFDtY1K+aonYaPyejoRD4Diisulm6Qim5mSs9aDJY7f+lz5Sw5FMTuSiv5co0aedxcnMllJ1OuLSQoeq1GieHAsEhmpc93My4hojkJ5RevynWamIFAcGEdQZoUDLoV8YSAEB82o0u6UtdXo7NBw8jDfhlqOILjdVNqMyzvK5Fi85YytR7WXFaxT/CY0nfIQCheK5sSkZFESuOZSh53Ksc6AMtcRuDHGLfbzU5fqZGzfnOmjqyUYShW1KyxNjKPs+buIfu2w0forUQhS3cRkvYzevt3a15/zNiGPB4K7M8rB3uJNlwZWWMXg5QY0R+OecFcxBzKKNqj+iC+Pks+EVMP7uZfRm0rKd90koNOrWpwpP9B3KVFTvGXFxWy9O0meALV4Y8DSbcAiFyn6moSa5KP4ehzBNLUUrRQaBmcrt/tA9OK9/jcVZndCHDPAzpjNj1VBLPSIMmGgnAQU2RYLrBhW+d44SVNgi+t8HSwrRFy7r0UxPW2w+mq5Bh0yvNFCKwC51kX4sH/ENNRzrns+xsCgGaXVJLo8mtvTeDSBwFXzKPqCL8o5ormCcOWjJ+2kZ6qNTAARgqDTxgjK5f5pSzgg2KUW2J6ughbA7NGB0/HpAH X-Forefront-Antispam-Report: CIP:149.199.62.198; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:xsj-pvapexch01.xlnx.xilinx.com; PTR:unknown-62-198.xilinx.com; CAT:NONE; SFS:(4636009)(396003)(346002)(39860400002)(136003)(376002)(46966006)(9786002)(478600001)(110136005)(8936002)(7636003)(26005)(316002)(82310400003)(70586007)(82740400003)(36756003)(83380400001)(36906005)(186003)(2906002)(2616005)(6666004)(107886003)(7696005)(44832011)(70206006)(47076005)(4326008)(8676002)(356005)(54906003)(5660300002)(336012)(426003)(102446001); DIR:OUT; SFP:1101; X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Jan 2021 14:28:05.2390 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2b52d6e3-5916-4a09-03c5-08d8c4621780 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c; Ip=[149.199.62.198]; Helo=[xsj-pvapexch01.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: CY1NAM02FT042.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN6PR02MB4606 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210129_092814_353226_C14116E5 X-CRM114-Status: GOOD ( 13.56 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-gpio@vger.kernel.org, Srinivas Neeli , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, git@xilinx.com Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Changed spinlock array to single. It is preparation for irq support which is shared between two channels that's why spinlock should be only one. Signed-off-by: Srinivas Neeli Reviewed-by: Linus Walleij --- Changes in V5: -None Changes in V4: -None. Changes in V3: -Created new patch for spinlock changes. --- drivers/gpio/gpio-xilinx.c | 25 ++++++++++++------------- 1 file changed, 12 insertions(+), 13 deletions(-) diff --git a/drivers/gpio/gpio-xilinx.c b/drivers/gpio/gpio-xilinx.c index d010a63d5d15..f88db56543c2 100644 --- a/drivers/gpio/gpio-xilinx.c +++ b/drivers/gpio/gpio-xilinx.c @@ -47,7 +47,7 @@ struct xgpio_instance { unsigned int gpio_width[2]; u32 gpio_state[2]; u32 gpio_dir[2]; - spinlock_t gpio_lock[2]; + spinlock_t gpio_lock; /* For serializing operations */ struct clk *clk; }; @@ -113,7 +113,7 @@ static void xgpio_set(struct gpio_chip *gc, unsigned int gpio, int val) int index = xgpio_index(chip, gpio); int offset = xgpio_offset(chip, gpio); - spin_lock_irqsave(&chip->gpio_lock[index], flags); + spin_lock_irqsave(&chip->gpio_lock, flags); /* Write to GPIO signal and set its direction to output */ if (val) @@ -124,7 +124,7 @@ static void xgpio_set(struct gpio_chip *gc, unsigned int gpio, int val) xgpio_writereg(chip->regs + XGPIO_DATA_OFFSET + xgpio_regoffset(chip, gpio), chip->gpio_state[index]); - spin_unlock_irqrestore(&chip->gpio_lock[index], flags); + spin_unlock_irqrestore(&chip->gpio_lock, flags); } /** @@ -144,7 +144,7 @@ static void xgpio_set_multiple(struct gpio_chip *gc, unsigned long *mask, int index = xgpio_index(chip, 0); int offset, i; - spin_lock_irqsave(&chip->gpio_lock[index], flags); + spin_lock_irqsave(&chip->gpio_lock, flags); /* Write to GPIO signals */ for (i = 0; i < gc->ngpio; i++) { @@ -155,9 +155,9 @@ static void xgpio_set_multiple(struct gpio_chip *gc, unsigned long *mask, xgpio_writereg(chip->regs + XGPIO_DATA_OFFSET + index * XGPIO_CHANNEL_OFFSET, chip->gpio_state[index]); - spin_unlock_irqrestore(&chip->gpio_lock[index], flags); + spin_unlock_irqrestore(&chip->gpio_lock, flags); index = xgpio_index(chip, i); - spin_lock_irqsave(&chip->gpio_lock[index], flags); + spin_lock_irqsave(&chip->gpio_lock, flags); } if (__test_and_clear_bit(i, mask)) { offset = xgpio_offset(chip, i); @@ -171,7 +171,7 @@ static void xgpio_set_multiple(struct gpio_chip *gc, unsigned long *mask, xgpio_writereg(chip->regs + XGPIO_DATA_OFFSET + index * XGPIO_CHANNEL_OFFSET, chip->gpio_state[index]); - spin_unlock_irqrestore(&chip->gpio_lock[index], flags); + spin_unlock_irqrestore(&chip->gpio_lock, flags); } /** @@ -190,14 +190,14 @@ static int xgpio_dir_in(struct gpio_chip *gc, unsigned int gpio) int index = xgpio_index(chip, gpio); int offset = xgpio_offset(chip, gpio); - spin_lock_irqsave(&chip->gpio_lock[index], flags); + spin_lock_irqsave(&chip->gpio_lock, flags); /* Set the GPIO bit in shadow register and set direction as input */ chip->gpio_dir[index] |= BIT(offset); xgpio_writereg(chip->regs + XGPIO_TRI_OFFSET + xgpio_regoffset(chip, gpio), chip->gpio_dir[index]); - spin_unlock_irqrestore(&chip->gpio_lock[index], flags); + spin_unlock_irqrestore(&chip->gpio_lock, flags); return 0; } @@ -221,7 +221,7 @@ static int xgpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val) int index = xgpio_index(chip, gpio); int offset = xgpio_offset(chip, gpio); - spin_lock_irqsave(&chip->gpio_lock[index], flags); + spin_lock_irqsave(&chip->gpio_lock, flags); /* Write state of GPIO signal */ if (val) @@ -236,7 +236,7 @@ static int xgpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val) xgpio_writereg(chip->regs + XGPIO_TRI_OFFSET + xgpio_regoffset(chip, gpio), chip->gpio_dir[index]); - spin_unlock_irqrestore(&chip->gpio_lock[index], flags); + spin_unlock_irqrestore(&chip->gpio_lock, flags); return 0; } @@ -312,7 +312,7 @@ static int xgpio_probe(struct platform_device *pdev) if (of_property_read_u32(np, "xlnx,gpio-width", &chip->gpio_width[0])) chip->gpio_width[0] = 32; - spin_lock_init(&chip->gpio_lock[0]); + spin_lock_init(&chip->gpio_lock); if (of_property_read_u32(np, "xlnx,is-dual", &is_dual)) is_dual = 0; @@ -336,7 +336,6 @@ static int xgpio_probe(struct platform_device *pdev) &chip->gpio_width[1])) chip->gpio_width[1] = 32; - spin_lock_init(&chip->gpio_lock[1]); } chip->gc.base = -1; -- 2.7.4 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel