From: Anshuman Khandual <anshuman.khandual@arm.com>
To: linux-arm-kernel@lists.infradead.org
Cc: mark.rutland@arm.com, Andre.Przywara@arm.com,
Anshuman Khandual <anshuman.khandual@arm.com>,
james.morse@arm.com, Suzuki.Poulose@arm.com
Subject: [boot-wrapper] [PATCH] aarch64: Enable TRBE for the non-secure world
Date: Thu, 11 Feb 2021 16:56:37 +0530 [thread overview]
Message-ID: <1613042797-13109-1-git-send-email-anshuman.khandual@arm.com> (raw)
MDCR_EL3.NSTB resets to an UNKNOWN value. Configure it to allow the trace
buffer to use non-secure memory and to permit direct register accesses from
the non-secure world. Before that, just check AA64DFR0_EL1.TraceBuffer and
make sure TRBE is implemented. We still continue to reset MDCR_EL3 register
to zero with the exception of MDCR_EL3.NSPB and MDCR_EL3.NSTB.
Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
---
arch/aarch64/boot.S | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/aarch64/boot.S b/arch/aarch64/boot.S
index 37f4b98..e47cf59 100644
--- a/arch/aarch64/boot.S
+++ b/arch/aarch64/boot.S
@@ -71,6 +71,14 @@ _start:
ldr x1, =(0x3 << 12)
orr x0, x0, x1
+1: mrs x1, id_aa64dfr0_el1
+ ubfx x1, x1, #44, #4
+ cbz x1, 1f
+
+ // Enable TRBE for the non-secure world.
+ ldr x1, =(0x3 << 24)
+ orr x0, x0, x1
+
1: msr mdcr_el3, x0 // Disable traps to EL3
mrs x0, id_aa64pfr0_el1
--
2.7.4
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next reply other threads:[~2021-02-11 11:28 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-02-11 11:26 Anshuman Khandual [this message]
2021-02-12 14:31 ` [boot-wrapper] [PATCH] aarch64: Enable TRBE for the non-secure world Alexandru Elisei
2021-02-12 15:44 ` Suzuki K Poulose
2021-02-12 17:28 ` Alexandru Elisei
2021-02-12 17:33 ` Alexandru Elisei
2021-02-25 18:33 ` Mark Rutland
2021-02-25 18:30 ` Mark Rutland
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