From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.0 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A419EC433C1 for ; Tue, 23 Mar 2021 11:37:02 +0000 (UTC) Received: from desiato.infradead.org (desiato.infradead.org [90.155.92.199]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 48627619B2 for ; Tue, 23 Mar 2021 11:37:02 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 48627619B2 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=mediatek.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=desiato.20200630; h=Sender:Content-Transfer-Encoding :Content-Type:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-ID:Date: Subject:CC:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=W4j/OARBNsF/zYoOCwJjEvudUo7eOwOqNbKQgJ6v8LA=; b=Xx9iH8p6RZD2w894prC85zlOH tvFczMR/Ryum7rsEZXRPE/aoeBKZWezuhYjJSsQ/6E2GmcVta5WBtZ7GAp94nIPLxfqPSmLIWE9R1 Up95e9UxP46Jj2lgzvCQu9mohxFmkn1O34IewsfkHCNp6e0RYvgQKSMb8VouNmtw/5zvzfhdVcQvF 0mfphoYc7bc+KvvtkpeyZFu/dEtrbuBvnBoT+Z50xhiCAhHbT/Gq9l52Dpwvkw80F+Utcs35oImPf Jv+WZQSNbo5GdTtQq1yMlKCpsloug42TBojReimaLSlQ0woxRX8lgCRskdkgWWpy/wjhveaukGAZ0 QdNYMFAIg==; Received: from localhost ([::1] helo=desiato.infradead.org) by desiato.infradead.org with esmtp (Exim 4.94 #2 (Red Hat Linux)) id 1lOfIt-00Eic8-8n; Tue, 23 Mar 2021 11:34:31 +0000 Received: from mailgw01.mediatek.com ([216.200.240.184]) by desiato.infradead.org with esmtps (Exim 4.94 #2 (Red Hat Linux)) id 1lOfId-00EiXm-Kr; Tue, 23 Mar 2021 11:34:19 +0000 X-UUID: 8648e9a103ae4d65a854e06d24fcf66d-20210323 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=VUjEKEUOSLh//gC0dXPpk/7IKS2KMuv+5PyRzSyK4Ts=; b=fnOc3fWb6EWxa5XEtJEU/rJ1ugh4hAn51fxnkjrOzUAN4NPx23exci147WWJ6ZQ0DwiP9FTDRnjMjfX2AuRlyusXQQWGhbmig/FhLyyjQyXIkx1fvFRhKqeHo7fNTlWCgvT/+3zeaBoLoZbJLkIR7flG+XyNW2/xCdVmEjgSAZw=; X-UUID: 8648e9a103ae4d65a854e06d24fcf66d-20210323 Received: from mtkcas67.mediatek.inc [(172.29.193.45)] by mailgw01.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 804033606; Tue, 23 Mar 2021 03:34:07 -0800 Received: from mtkmbs07n1.mediatek.inc (172.21.101.16) by MTKMBS62DR.mediatek.inc (172.29.94.18) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 23 Mar 2021 04:34:06 -0700 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 23 Mar 2021 19:34:04 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 23 Mar 2021 19:34:04 +0800 From: Andrew-sh.Cheng To: MyungJoo Ham , Kyungmin Park , Chanwoo Choi , "Rob Herring" , Mark Rutland , "Matthias Brugger" , "Rafael J. Wysocki" , Viresh Kumar , Nishanth Menon , "Stephen Boyd" , Liam Girdwood , Mark Brown CC: , , , , , , Andrew-sh.Cheng Subject: [PATCH V8 2/8] cpufreq: mediatek: Enable clock and regulator Date: Tue, 23 Mar 2021 19:33:55 +0800 Message-ID: <1616499241-4906-3-git-send-email-andrew-sh.cheng@mediatek.com> X-Mailer: git-send-email 1.8.1.1.dirty In-Reply-To: <1616499241-4906-1-git-send-email-andrew-sh.cheng@mediatek.com> References: <1616499241-4906-1-git-send-email-andrew-sh.cheng@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210323_113416_229909_8DA97D61 X-CRM114-Status: GOOD ( 14.05 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: "Andrew-sh.Cheng" Need to enable regulator, so that the max/min requested value will be recorded even it is not applied right away. Intermediate clock is not always enabled by ccf in different projects, so cpufreq should enable it by itself. Signed-off-by: Andrew-sh.Cheng --- drivers/cpufreq/mediatek-cpufreq.c | 33 +++++++++++++++++++++++++++++---- 1 file changed, 29 insertions(+), 4 deletions(-) diff --git a/drivers/cpufreq/mediatek-cpufreq.c b/drivers/cpufreq/mediatek-cpufreq.c index f2e491b25b07..432368707ea6 100644 --- a/drivers/cpufreq/mediatek-cpufreq.c +++ b/drivers/cpufreq/mediatek-cpufreq.c @@ -350,6 +350,11 @@ static int mtk_cpu_dvfs_info_init(struct mtk_cpu_dvfs_info *info, int cpu) ret = PTR_ERR(proc_reg); goto out_free_resources; } + ret = regulator_enable(proc_reg); + if (ret) { + pr_warn("enable vproc for cpu%d fail\n", cpu); + goto out_free_resources; + } /* Both presence and absence of sram regulator are valid cases. */ sram_reg = regulator_get_exclusive(cpu_dev, "sram"); @@ -368,13 +373,21 @@ static int mtk_cpu_dvfs_info_init(struct mtk_cpu_dvfs_info *info, int cpu) goto out_free_resources; } + ret = clk_prepare_enable(cpu_clk); + if (ret) + goto out_free_opp_table; + + ret = clk_prepare_enable(inter_clk); + if (ret) + goto out_disable_mux_clock; + /* Search a safe voltage for intermediate frequency. */ rate = clk_get_rate(inter_clk); opp = dev_pm_opp_find_freq_ceil(cpu_dev, &rate); if (IS_ERR(opp)) { pr_err("failed to get intermediate opp for cpu%d\n", cpu); ret = PTR_ERR(opp); - goto out_free_opp_table; + goto out_disable_inter_clock; } info->intermediate_voltage = dev_pm_opp_get_voltage(opp); dev_pm_opp_put(opp); @@ -393,6 +406,12 @@ static int mtk_cpu_dvfs_info_init(struct mtk_cpu_dvfs_info *info, int cpu) return 0; +out_disable_inter_clock: + clk_disable_unprepare(inter_clk); + +out_disable_mux_clock: + clk_disable_unprepare(cpu_clk); + out_free_opp_table: dev_pm_opp_of_cpumask_remove_table(&info->cpus); @@ -411,14 +430,20 @@ static int mtk_cpu_dvfs_info_init(struct mtk_cpu_dvfs_info *info, int cpu) static void mtk_cpu_dvfs_info_release(struct mtk_cpu_dvfs_info *info) { - if (!IS_ERR(info->proc_reg)) + if (!IS_ERR(info->proc_reg)) { + regulator_disable(info->proc_reg); regulator_put(info->proc_reg); + } if (!IS_ERR(info->sram_reg)) regulator_put(info->sram_reg); - if (!IS_ERR(info->cpu_clk)) + if (!IS_ERR(info->cpu_clk)) { + clk_disable_unprepare(info->cpu_clk); clk_put(info->cpu_clk); - if (!IS_ERR(info->inter_clk)) + } + if (!IS_ERR(info->inter_clk)) { + clk_disable_unprepare(info->inter_clk); clk_put(info->inter_clk); + } dev_pm_opp_of_cpumask_remove_table(&info->cpus); } -- 2.12.5 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel