* Re: [PATCH 2/6] dt-bindings: pinctrl: mt8195: add binding document
[not found] ` <20210329065047.8388-3-zhiyong.tao@mediatek.com>
@ 2021-03-29 13:03 ` Rob Herring
2021-03-29 13:58 ` Rob Herring
1 sibling, 0 replies; 3+ messages in thread
From: Rob Herring @ 2021-03-29 13:03 UTC (permalink / raw)
To: Zhiyong Tao
Cc: linux-mediatek, linux-arm-kernel, hui.liu, sean.wang, erin.lo,
jg_poxu, devicetree, linux-kernel, mark.rutland, biao.huang,
srv_heupstream, matthias.bgg, linus.walleij, sean.wang,
eddie.huang, hongzhou.yang, sj.huang, seiya.wang, linux-gpio,
robh+dt
On Mon, 29 Mar 2021 14:50:43 +0800, Zhiyong Tao wrote:
> The commit adds mt8195 compatible node in binding document.
>
> Signed-off-by: Zhiyong Tao <zhiyong.tao@mediatek.com>
> ---
> .../bindings/pinctrl/pinctrl-mt8195.yaml | 152 ++++++++++++++++++
> 1 file changed, 152 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/pinctrl/pinctrl-mt8195.yaml
>
My bot found errors running 'make dt_binding_check' on your patch:
yamllint warnings/errors:
dtschema/dtc warnings/errors:
Documentation/devicetree/bindings/pinctrl/pinctrl-mt8195.example.dts:19:18: fatal error: dt-bindings/pinctrl/mt8195-pinfunc.h: No such file or directory
19 | #include <dt-bindings/pinctrl/mt8195-pinfunc.h>
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
compilation terminated.
make[1]: *** [scripts/Makefile.lib:349: Documentation/devicetree/bindings/pinctrl/pinctrl-mt8195.example.dt.yaml] Error 1
make[1]: *** Waiting for unfinished jobs....
make: *** [Makefile:1380: dt_binding_check] Error 2
See https://patchwork.ozlabs.org/patch/1459436
This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit.
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH 2/6] dt-bindings: pinctrl: mt8195: add binding document
[not found] ` <20210329065047.8388-3-zhiyong.tao@mediatek.com>
2021-03-29 13:03 ` [PATCH 2/6] dt-bindings: pinctrl: mt8195: add binding document Rob Herring
@ 2021-03-29 13:58 ` Rob Herring
2021-03-30 9:09 ` zhiyong tao
1 sibling, 1 reply; 3+ messages in thread
From: Rob Herring @ 2021-03-29 13:58 UTC (permalink / raw)
To: Zhiyong Tao
Cc: linus.walleij, mark.rutland, matthias.bgg, sean.wang,
srv_heupstream, hui.liu, eddie.huang, jg_poxu, biao.huang,
hongzhou.yang, erin.lo, sean.wang, seiya.wang, sj.huang,
devicetree, linux-kernel, linux-arm-kernel, linux-mediatek,
linux-gpio
On Mon, Mar 29, 2021 at 02:50:43PM +0800, Zhiyong Tao wrote:
> The commit adds mt8195 compatible node in binding document.
>
> Signed-off-by: Zhiyong Tao <zhiyong.tao@mediatek.com>
> ---
> .../bindings/pinctrl/pinctrl-mt8195.yaml | 152 ++++++++++++++++++
> 1 file changed, 152 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/pinctrl/pinctrl-mt8195.yaml
>
> diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-mt8195.yaml b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt8195.yaml
> new file mode 100644
> index 000000000000..7915b9568c29
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt8195.yaml
> @@ -0,0 +1,152 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/pinctrl/pinctrl-mt8195.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Mediatek MT8195 Pin Controller
> +
> +maintainers:
> + - Sean Wang <sean.wang@mediatek.com>
> +
> +description: |
> + The Mediatek's Pin controller is used to control SoC pins.
> +
> +properties:
> + compatible:
> + const: mediatek,mt8195-pinctrl
> +
> + gpio-controller: true
> +
> + '#gpio-cells':
> + description: |
> + Number of cells in GPIO specifier. Since the generic GPIO binding is used,
> + the amount of cells must be specified as 2. See the below
> + mentioned gpio binding representation for description of particular cells.
> + const: 2
> +
> + gpio-ranges:
> + description: gpio valid number range.
> + maxItems: 1
> +
> + reg:
> + description: |
> + Physical address base for gpio base registers. There are 8 GPIO
> + physical address base in mt8195.
> + maxItems: 8
> +
> + reg-names:
> + description: |
> + Gpio base register names.
> + maxItems: 8
> +
> + interrupt-controller: true
> +
> + '#interrupt-cells':
> + const: 2
> +
> + interrupts:
> + description: The interrupt outputs to sysirq.
> + maxItems: 1
> +
> +#PIN CONFIGURATION NODES
> +patternProperties:
> + '^pins':
Normally we're doing '-pins$'.
> + type: object
> + description: |
> + A pinctrl node should contain at least one subnodes representing the
> + pinctrl groups available on the machine. Each subnode will list the
> + pins it needs, and how they should be configured, with regard to muxer
> + configuration, pullups, drive strength, input enable/disable and
> + input schmitt.
> + An example of using macro:
> + pincontroller {
> + /* GPIO0 set as multifunction GPIO0 */
> + state_0_node_a {
Use the node name pattern defined.
> + pinmux = <PINMUX_GPIO0__FUNC_GPIO0>;
> + };
> + /* GPIO1 set as multifunction CLKM1 */
> + state_0_node_b {
> + pinmux = <PINMUX_GPIO1__FUNC_CLKM1>;
> + };
> + };
> + $ref: "pinmux-node.yaml"
> +
> + properties:
> + pinmux:
> + description: |
> + Integer array, represents gpio pin number and mux setting.
> + Supported pin number and mux varies for different SoCs, and are defined
> + as macros in dt-bindings/pinctrl/<soc>-pinfunc.h directly.
> +
> + drive-strength:
> + description: |
> + It can support some arguments, such as MTK_DRIVE_4mA, MTK_DRIVE_6mA, etc. See
> + dt-bindings/pinctrl/mt65xx.h. It can only support 2/4/6/8/10/12/14/16mA in mt8195.
> + enum: [2, 4, 6, 8, 10, 12, 14, 16]
> +
> + bias-pull-down: true
> +
> + bias-pull-up: true
> +
> + bias-disable: true
> +
> + output-high: true
> +
> + output-low: true
> +
> + input-enable: true
> +
> + input-disable: true
> +
> + input-schmitt-enable: true
> +
> + input-schmitt-disable: true
> +
> + required:
> + - pinmux
> +
> + additionalProperties: false
> +
> +required:
> + - compatible
> + - reg
> + - interrupts
> + - interrupt-controller
> + - '#interrupt-cells'
> + - gpio-controller
> + - '#gpio-cells'
> + - gpio-ranges
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/pinctrl/mt8195-pinfunc.h>
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> + pio: pinctrl@10005000 {
> + compatible = "mediatek,mt8195-pinctrl";
> + reg = <0x10005000 0x1000>,
> + <0x11d10000 0x1000>,
> + <0x11d30000 0x1000>,
> + <0x11d40000 0x1000>,
> + <0x11e20000 0x1000>,
> + <0x11e20000 0x1000>,
> + <0x11eb0000 0x1000>,
> + <0x11f40000 0x1000>,
> + <0x1000b000 0x1000>;
> + reg-names = "iocfg0", "iocfg_bm", "iocfg_bl",
> + "iocfg_br", "iocfg_lm", "iocfg_rb",
> + "iocfg_tl", "eint";
> + gpio-controller;
> + #gpio-cells = <2>;
> + gpio-ranges = <&pio 0 0 144>;
> + interrupt-controller;
> + interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH 0>;
> + #interrupt-cells = <2>;
> +
> + pins {
> + pinmux = <PINMUX_GPIO0__FUNC_GPIO0>;
> + output-low;
> + };
> + };
> --
> 2.18.0
>
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH 2/6] dt-bindings: pinctrl: mt8195: add binding document
2021-03-29 13:58 ` Rob Herring
@ 2021-03-30 9:09 ` zhiyong tao
0 siblings, 0 replies; 3+ messages in thread
From: zhiyong tao @ 2021-03-30 9:09 UTC (permalink / raw)
To: Rob Herring
Cc: linus.walleij, mark.rutland, matthias.bgg, sean.wang,
srv_heupstream, hui.liu, eddie.huang, jg_poxu, biao.huang,
hongzhou.yang, erin.lo, sean.wang, seiya.wang, sj.huang,
devicetree, linux-kernel, linux-arm-kernel, linux-mediatek,
linux-gpio
On Mon, 2021-03-29 at 08:58 -0500, Rob Herring wrote:
> On Mon, Mar 29, 2021 at 02:50:43PM +0800, Zhiyong Tao wrote:
> > The commit adds mt8195 compatible node in binding document.
> >
> > Signed-off-by: Zhiyong Tao <zhiyong.tao@mediatek.com>
> > ---
> > .../bindings/pinctrl/pinctrl-mt8195.yaml | 152 ++++++++++++++++++
> > 1 file changed, 152 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/pinctrl/pinctrl-mt8195.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-mt8195.yaml b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt8195.yaml
> > new file mode 100644
> > index 000000000000..7915b9568c29
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt8195.yaml
> > @@ -0,0 +1,152 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/pinctrl/pinctrl-mt8195.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Mediatek MT8195 Pin Controller
> > +
> > +maintainers:
> > + - Sean Wang <sean.wang@mediatek.com>
> > +
> > +description: |
> > + The Mediatek's Pin controller is used to control SoC pins.
> > +
> > +properties:
> > + compatible:
> > + const: mediatek,mt8195-pinctrl
> > +
> > + gpio-controller: true
> > +
> > + '#gpio-cells':
> > + description: |
> > + Number of cells in GPIO specifier. Since the generic GPIO binding is used,
> > + the amount of cells must be specified as 2. See the below
> > + mentioned gpio binding representation for description of particular cells.
> > + const: 2
> > +
> > + gpio-ranges:
> > + description: gpio valid number range.
> > + maxItems: 1
> > +
> > + reg:
> > + description: |
> > + Physical address base for gpio base registers. There are 8 GPIO
> > + physical address base in mt8195.
> > + maxItems: 8
> > +
> > + reg-names:
> > + description: |
> > + Gpio base register names.
> > + maxItems: 8
> > +
> > + interrupt-controller: true
> > +
> > + '#interrupt-cells':
> > + const: 2
> > +
> > + interrupts:
> > + description: The interrupt outputs to sysirq.
> > + maxItems: 1
> > +
> > +#PIN CONFIGURATION NODES
> > +patternProperties:
> > + '^pins':
>
> Normally we're doing '-pins$'.
==> Thanks for your suggestion. we will change it in next version.
>
> > + type: object
> > + description: |
> > + A pinctrl node should contain at least one subnodes representing the
> > + pinctrl groups available on the machine. Each subnode will list the
> > + pins it needs, and how they should be configured, with regard to muxer
> > + configuration, pullups, drive strength, input enable/disable and
> > + input schmitt.
> > + An example of using macro:
> > + pincontroller {
> > + /* GPIO0 set as multifunction GPIO0 */
> > + state_0_node_a {
>
> Use the node name pattern defined.
==> Thanks for your suggestion. we will change it in next version.
>
> > + pinmux = <PINMUX_GPIO0__FUNC_GPIO0>;
> > + };
> > + /* GPIO1 set as multifunction CLKM1 */
> > + state_0_node_b {
> > + pinmux = <PINMUX_GPIO1__FUNC_CLKM1>;
> > + };
> > + };
> > + $ref: "pinmux-node.yaml"
> > +
> > + properties:
> > + pinmux:
> > + description: |
> > + Integer array, represents gpio pin number and mux setting.
> > + Supported pin number and mux varies for different SoCs, and are defined
> > + as macros in dt-bindings/pinctrl/<soc>-pinfunc.h directly.
> > +
> > + drive-strength:
> > + description: |
> > + It can support some arguments, such as MTK_DRIVE_4mA, MTK_DRIVE_6mA, etc. See
> > + dt-bindings/pinctrl/mt65xx.h. It can only support 2/4/6/8/10/12/14/16mA in mt8195.
> > + enum: [2, 4, 6, 8, 10, 12, 14, 16]
> > +
> > + bias-pull-down: true
> > +
> > + bias-pull-up: true
> > +
> > + bias-disable: true
> > +
> > + output-high: true
> > +
> > + output-low: true
> > +
> > + input-enable: true
> > +
> > + input-disable: true
> > +
> > + input-schmitt-enable: true
> > +
> > + input-schmitt-disable: true
> > +
> > + required:
> > + - pinmux
> > +
> > + additionalProperties: false
> > +
> > +required:
> > + - compatible
> > + - reg
> > + - interrupts
> > + - interrupt-controller
> > + - '#interrupt-cells'
> > + - gpio-controller
> > + - '#gpio-cells'
> > + - gpio-ranges
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > + - |
> > + #include <dt-bindings/pinctrl/mt8195-pinfunc.h>
> > + #include <dt-bindings/interrupt-controller/arm-gic.h>
> > + pio: pinctrl@10005000 {
> > + compatible = "mediatek,mt8195-pinctrl";
> > + reg = <0x10005000 0x1000>,
> > + <0x11d10000 0x1000>,
> > + <0x11d30000 0x1000>,
> > + <0x11d40000 0x1000>,
> > + <0x11e20000 0x1000>,
> > + <0x11e20000 0x1000>,
> > + <0x11eb0000 0x1000>,
> > + <0x11f40000 0x1000>,
> > + <0x1000b000 0x1000>;
> > + reg-names = "iocfg0", "iocfg_bm", "iocfg_bl",
> > + "iocfg_br", "iocfg_lm", "iocfg_rb",
> > + "iocfg_tl", "eint";
> > + gpio-controller;
> > + #gpio-cells = <2>;
> > + gpio-ranges = <&pio 0 0 144>;
> > + interrupt-controller;
> > + interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH 0>;
> > + #interrupt-cells = <2>;
> > +
> > + pins {
> > + pinmux = <PINMUX_GPIO0__FUNC_GPIO0>;
> > + output-low;
> > + };
> > + };
> > --
> > 2.18.0
> >
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[not found] <20210329065047.8388-1-zhiyong.tao@mediatek.com>
[not found] ` <20210329065047.8388-3-zhiyong.tao@mediatek.com>
2021-03-29 13:03 ` [PATCH 2/6] dt-bindings: pinctrl: mt8195: add binding document Rob Herring
2021-03-29 13:58 ` Rob Herring
2021-03-30 9:09 ` zhiyong tao
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