From: Shaokun Zhang <zhangshaokun@hisilicon.com>
To: <linux-arm-kernel@lists.infradead.org>
Cc: Shaokun Zhang <zhangshaokun@hisilicon.com>,
Mark Rutland <mark.rutland@arm.com>,
Will Deacon <will@kernel.org>
Subject: [PATCH -next] arm64: perf: Fix hw_event_id check in __armv8_pmuv3_map_event
Date: Mon, 7 Jun 2021 15:19:03 +0800 [thread overview]
Message-ID: <1623050343-62397-1-git-send-email-zhangshaokun@hisilicon.com> (raw)
Raw event SW_INCR (0x0000) shall be included in this check, so fix it.
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Will Deacon <will@kernel.org>
Signed-off-by: Shaokun Zhang <zhangshaokun@hisilicon.com>
---
arch/arm64/kernel/perf_event.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c
index a661010308c0..fa2f60d09e15 100644
--- a/arch/arm64/kernel/perf_event.c
+++ b/arch/arm64/kernel/perf_event.c
@@ -1000,7 +1000,7 @@ static int __armv8_pmuv3_map_event(struct perf_event *event,
event->hw.flags |= ARMPMU_EVT_64BIT;
/* Only expose micro/arch events supported by this PMU */
- if ((hw_event_id > 0) && (hw_event_id < ARMV8_PMUV3_MAX_COMMON_EVENTS)
+ if ((hw_event_id >= 0) && (hw_event_id < ARMV8_PMUV3_MAX_COMMON_EVENTS)
&& test_bit(hw_event_id, armpmu->pmceid_bitmap)) {
return hw_event_id;
}
--
2.7.4
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next reply other threads:[~2021-06-07 7:21 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-07 7:19 Shaokun Zhang [this message]
2021-06-07 8:37 ` [PATCH -next] arm64: perf: Fix hw_event_id check in __armv8_pmuv3_map_event Mark Rutland
2021-06-07 10:39 ` Shaokun Zhang
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