From: CK Hu <ck.hu@mediatek.com>
To: Nancy.Lin <nancy.lin@mediatek.com>
Cc: Chun-Kuang Hu <chunkuang.hu@kernel.org>,
Philipp Zabel <p.zabel@pengutronix.de>,
David Airlie <airlied@linux.ie>, Daniel Vetter <daniel@ffwll.ch>,
Rob Herring <robh+dt@kernel.org>,
Matthias Brugger <matthias.bgg@gmail.com>,
"jason-jh . lin" <jason-jh.lin@mediatek.com>,
Yongqiang Niu <yongqiang.niu@mediatek.com>,
DRI Development <dri-devel@lists.freedesktop.org>,
"moderated list:ARM/Mediatek SoC support"
<linux-mediatek@lists.infradead.org>,
DTML <devicetree@vger.kernel.org>,
linux-kernel <linux-kernel@vger.kernel.org>,
Linux ARM <linux-arm-kernel@lists.infradead.org>,
<singo.chang@mediatek.com>,
srv_heupstream <srv_heupstream@mediatek.com>
Subject: Re: [PATCH v1 06/10] drm/mediatek: add ETHDR support for MT8195
Date: Thu, 22 Jul 2021 13:25:41 +0800 [thread overview]
Message-ID: <1626931541.16442.15.camel@mtksdaap41> (raw)
In-Reply-To: <3f8b55c75f97e46901c9380fefd2c15a8c5a2a72.camel@mediatek.com>
Hi, Nancy:
On Thu, 2021-07-22 at 09:32 +0800, Nancy.Lin wrote:
> Hi Chun-Kuang,
>
> On Mon, 2021-07-19 at 07:56 +0800, Chun-Kuang Hu wrote:
> > Hi, Nancy:
> >
> > Nancy.Lin <nancy.lin@mediatek.com> 於 2021年7月17日 週六 下午5:04寫道:
> > >
> > > Add ETHDR module files:
> > > ETHDR is designed for HDR video and graphics conversion in the
> > > external
> > > display path. It handles multiple HDR input types and performs tone
> > > mapping, color space/color format conversion, and then combines
> > > different layers, output the required HDR or SDR signal to the
> > > subsequent display path.
> > >
> > > Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> > > ---
> > > drivers/gpu/drm/mediatek/Makefile | 3 +-
> > > drivers/gpu/drm/mediatek/mtk_disp_drv.h | 8 +
> > > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 11 +
> > > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 +
> > > drivers/gpu/drm/mediatek/mtk_drm_drv.c | 4 +
> > > drivers/gpu/drm/mediatek/mtk_drm_drv.h | 1 +
> > > drivers/gpu/drm/mediatek/mtk_ethdr.c | 537
> > > ++++++++++++++++++++
> > > drivers/gpu/drm/mediatek/mtk_ethdr.h | 20 +
> > > 8 files changed, 584 insertions(+), 1 deletion(-)
> > > create mode 100644 drivers/gpu/drm/mediatek/mtk_ethdr.c
> > > create mode 100644 drivers/gpu/drm/mediatek/mtk_ethdr.h
> > >
> > > +
> > > +void mtk_ethdr_layer_on(struct device *dev, unsigned int idx,
> > > + struct cmdq_pkt *cmdq_pkt)
> > > +{
> > > + struct mtk_ethdr *priv = dev_get_drvdata(dev);
> > > + struct mtk_ethdr_comp *mixer = &priv-
> > > >ethdr_comp[ETHDR_MIXER];
> > > +
> > > + dev_dbg(dev, "%s+ idx:%d", __func__, idx);
> > > +
> > > + if (idx < 4)
> > > + mtk_ddp_write_mask(cmdq_pkt, BIT(idx), &mixer-
> > > >cmdq_base,
> > > + mixer->regs, MIX_SRC_CON,
> > > BIT(idx));
> > > +}
> > > +
> > > +void mtk_ethdr_layer_off(struct device *dev, unsigned int idx,
> > > + struct cmdq_pkt *cmdq_pkt)
> > > +{
> > > + struct mtk_ethdr *priv = dev_get_drvdata(dev);
> > > + struct mtk_ethdr_comp *mixer = &priv-
> > > >ethdr_comp[ETHDR_MIXER];
> > > +
> > > + dev_dbg(dev, "%s+ idx:%d", __func__, idx);
> > > +
> > > + switch (idx) {
> > > + case 0:
> > > + mtk_ddp_write_mask(cmdq_pkt, 0, &mixer->cmdq_base,
> > > + mixer->regs, MIX_L0_SRC_SIZE,
> > > ~0);
> > > + break;
> > > + case 1:
> > > + mtk_ddp_write_mask(cmdq_pkt, 0, &mixer->cmdq_base,
> > > + mixer->regs, MIX_L1_SRC_SIZE,
> > > ~0);
> > > + break;
> > > + case 2:
> > > + mtk_ddp_write_mask(cmdq_pkt, 0, &mixer->cmdq_base,
> > > + mixer->regs, MIX_L2_SRC_SIZE,
> > > ~0);
> > > + break;
> > > + case 3:
> > > + mtk_ddp_write_mask(cmdq_pkt, 0, &mixer->cmdq_base,
> > > + mixer->regs, MIX_L3_SRC_SIZE,
> > > ~0);
> > > + break;
> > > + default:
> > > + dev_dbg(dev, "%s Wrong layer ID\n", __func__);
> > > + break;
> > > + }
> >
> > Why not just
> >
> > mtk_ddp_write_mask(cmdq_pkt, 0, &mixer->cmdq_base,
> > mixer->regs, MIX_SRC_CON,
> > BIT(idx));
> >
>
> There are two modes in Mixer.
> 1. Background relay mode: all layers off
> 2. Normal mix mode: at least one layer on
> The timing of the two modes is different, so keep using the normal mix
> mode.
> Just set the layer region to 0 when the layer off.
layer_on() and layer_off() does different things. Comparing before turn
on a layer with after turn on->off a layer, the register setting are
different. I would like just restore the register.
Regards,
CK
>
> > > +}
> > > +
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next prev parent reply other threads:[~2021-07-22 5:28 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-07-17 9:03 [PATCH v1 00/10] Add MediaTek SoC DRM (vdosys1) support for mt8195 Nancy.Lin
2021-07-17 9:03 ` [PATCH v1 01/10] dt-bindings: mediatek: add pseudo-ovl definition " Nancy.Lin
2021-07-18 23:22 ` Chun-Kuang Hu
2021-07-22 0:59 ` Nancy.Lin
2021-07-17 9:04 ` [PATCH v1 02/10] dt-bindings: mediatek: add ethdr " Nancy.Lin
2021-07-17 9:04 ` [PATCH v1 03/10] arm64: dts: mt8195: add display node for vdosys1 Nancy.Lin
2021-07-17 9:04 ` [PATCH v1 04/10] soc: mediatek: add mtk-mmsys support for mt8195 vdosys1 Nancy.Lin
2021-07-17 9:04 ` [PATCH v1 05/10] soc: mediatek: add mtk-mutex " Nancy.Lin
2021-07-17 9:04 ` [PATCH v1 06/10] drm/mediatek: add ETHDR support for MT8195 Nancy.Lin
2021-07-18 23:56 ` Chun-Kuang Hu
2021-07-22 1:32 ` Nancy.Lin
2021-07-22 5:25 ` CK Hu [this message]
2021-07-17 9:04 ` [PATCH v1 07/10] drm/mediatek: add pseudo ovl " Nancy.Lin
2021-07-20 5:57 ` CK Hu
2021-07-17 9:04 ` [PATCH v1 08/10] drm/mediatek: add merge vblank " Nancy.Lin
2021-07-17 9:04 ` [PATCH v1 09/10] soc: mediatek: mmsys: add new mtk_mmsys struct member to store drm data Nancy.Lin
2021-07-17 9:04 ` [PATCH v1 10/10] drm/mediatek: add mediatek-drm of vdosys1 support for MT8195 Nancy.Lin
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