From: Anshuman Khandual <anshuman.khandual@arm.com>
To: linux-arm-kernel@lists.infradead.org
Cc: Anshuman Khandual <anshuman.khandual@arm.com>,
Catalin Marinas <catalin.marinas@arm.com>,
Will Deacon <will@kernel.org>,
Mathieu Poirier <mathieu.poirier@linaro.org>,
Suzuki Poulose <suzuki.poulose@arm.com>,
coresight@lists.linaro.org, linux-doc@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: [PATCH V3 1/7] arm64: Add Cortex-A510 CPU part definition
Date: Tue, 11 Jan 2022 09:09:00 +0530 [thread overview]
Message-ID: <1641872346-3270-2-git-send-email-anshuman.khandual@arm.com> (raw)
In-Reply-To: <1641872346-3270-1-git-send-email-anshuman.khandual@arm.com>
Add the CPU Partnumbers for the new Arm designs.
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: Suzuki Poulose <suzuki.poulose@arm.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
---
arch/arm64/include/asm/cputype.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h
index 19b8441aa8f2..e8fdc10395b6 100644
--- a/arch/arm64/include/asm/cputype.h
+++ b/arch/arm64/include/asm/cputype.h
@@ -73,6 +73,7 @@
#define ARM_CPU_PART_CORTEX_A76 0xD0B
#define ARM_CPU_PART_NEOVERSE_N1 0xD0C
#define ARM_CPU_PART_CORTEX_A77 0xD0D
+#define ARM_CPU_PART_CORTEX_A510 0xD46
#define ARM_CPU_PART_CORTEX_A710 0xD47
#define ARM_CPU_PART_NEOVERSE_N2 0xD49
@@ -115,6 +116,7 @@
#define MIDR_CORTEX_A76 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A76)
#define MIDR_NEOVERSE_N1 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N1)
#define MIDR_CORTEX_A77 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A77)
+#define MIDR_CORTEX_A510 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A510)
#define MIDR_CORTEX_A710 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A710)
#define MIDR_NEOVERSE_N2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N2)
#define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX)
--
2.25.1
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next prev parent reply other threads:[~2022-01-11 3:44 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-01-11 3:38 [PATCH V3 0/7] coresight: trbe: Workaround Cortex-A510 erratas Anshuman Khandual
2022-01-11 3:39 ` Anshuman Khandual [this message]
2022-01-11 3:39 ` [PATCH V3 2/7] arm64: errata: Add detection for TRBE ignored system register writes Anshuman Khandual
2022-01-11 3:39 ` [PATCH V3 3/7] arm64: errata: Add detection for TRBE invalid prohibited states Anshuman Khandual
2022-01-11 3:39 ` [PATCH V3 4/7] arm64: errata: Add detection for TRBE trace data corruption Anshuman Khandual
2022-01-11 3:39 ` [PATCH V3 5/7] coresight: trbe: Work around the ignored system register writes Anshuman Khandual
2022-01-11 3:39 ` [PATCH V3 6/7] coresight: trbe: Work around the invalid prohibited states Anshuman Khandual
2022-01-11 3:39 ` [PATCH V3 7/7] coresight: trbe: Work around the trace data corruption Anshuman Khandual
2022-01-25 3:21 ` [PATCH V3 0/7] coresight: trbe: Workaround Cortex-A510 erratas Anshuman Khandual
2022-01-25 10:02 ` Suzuki K Poulose
2022-01-25 10:46 ` Anshuman Khandual
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