[PATCH 0/2] coresight: trbe: Update existing errata for Cortex-X2

[PATCH 0/2] coresight: trbe: Update existing errata for Cortex-X2

[Anshuman Khandual]

Errata ARM64_ERRATUM_[2119858|2224489] also affect some Cortex-X2 ranges as
well. This series updates the errata definition and detection as required.
This series applies on v5.16.

Relevant identification document can be found here.

https://developer.arm.com/documentation/101803/0200/AArch64-system-registers/
AArch64-identification-register-summary/MIDR-EL1--Main-ID-Register

Relevant errata document can be found here.

https://developer.arm.com/documentation/SDEN1775100

Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Cc: Suzuki Poulose <suzuki.poulose@arm.com>
Cc: coresight@lists.linaro.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org

Anshuman Khandual (2):
  arm64: Add Cortex-X2 CPU part definition
  arm64: errata: Update ARM64_ERRATUM_[2119858|2224489] with Cortex-X2 ranges

 arch/arm64/Kconfig               | 12 ++++++------
 arch/arm64/include/asm/cputype.h |  2 ++
 arch/arm64/kernel/cpu_errata.c   |  2 ++
 3 files changed, 10 insertions(+), 6 deletions(-)

-- 
2.20.1


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[PATCH 1/2] arm64: Add Cortex-X2 CPU part definition

[Anshuman Khandual]

Add the CPU Partnumbers for the new Arm designs.

Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: Suzuki Poulose <suzuki.poulose@arm.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
---
 arch/arm64/include/asm/cputype.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h
index 19b8441aa8f2..657eeb06c784 100644
--- a/arch/arm64/include/asm/cputype.h
+++ b/arch/arm64/include/asm/cputype.h
@@ -74,6 +74,7 @@
 #define ARM_CPU_PART_NEOVERSE_N1	0xD0C
 #define ARM_CPU_PART_CORTEX_A77		0xD0D
 #define ARM_CPU_PART_CORTEX_A710	0xD47
+#define ARM_CPU_PART_CORTEX_X2		0xD48
 #define ARM_CPU_PART_NEOVERSE_N2	0xD49
 
 #define APM_CPU_PART_POTENZA		0x000
@@ -116,6 +117,7 @@
 #define MIDR_NEOVERSE_N1 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N1)
 #define MIDR_CORTEX_A77	MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A77)
 #define MIDR_CORTEX_A710 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A710)
+#define MIDR_CORTEX_X2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X2)
 #define MIDR_NEOVERSE_N2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N2)
 #define MIDR_THUNDERX	MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX)
 #define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX)
-- 
2.20.1


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Re: [PATCH 1/2] arm64: Add Cortex-X2 CPU part definition

[Arnd Bergmann]

On Wed, Jan 12, 2022 at 10:34 AM Anshuman Khandual
<anshuman.khandual@arm.com> wrote:
>
> Add the CPU Partnumbers for the new Arm designs.
>
> Cc: Catalin Marinas <catalin.marinas@arm.com>
> Cc: Will Deacon <will@kernel.org>
> Cc: Suzuki Poulose <suzuki.poulose@arm.com>
> Cc: linux-arm-kernel@lists.infradead.org
> Cc: linux-kernel@vger.kernel.org
> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
> ---
>  arch/arm64/include/asm/cputype.h | 2 ++
>  1 file changed, 2 insertions(+)
>
> diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h
> index 19b8441aa8f2..657eeb06c784 100644
> --- a/arch/arm64/include/asm/cputype.h
> +++ b/arch/arm64/include/asm/cputype.h
> @@ -74,6 +74,7 @@
>  #define ARM_CPU_PART_NEOVERSE_N1       0xD0C
>  #define ARM_CPU_PART_CORTEX_A77                0xD0D
>  #define ARM_CPU_PART_CORTEX_A710       0xD47
> +#define ARM_CPU_PART_CORTEX_X2         0xD48
>  #define ARM_CPU_PART_NEOVERSE_N2       0xD49

No objections to the patch, but would it be possible to just add all the missing
ones here to the degree that they are known already? I don't see any entries for
Cortex-A34, Cortex-A65AE, Cortex-A78, Cortex-A78C, Cortex-A78AE,
Neoverse-E1, Neoverse-V1, Cortex-X1, Cortex-X2, Cortex-A510, Cortex-A710
and Cortex-R82 among the Arm-designed cores that can run Linux, and there
are probably others that I missed going through the list.

        Arnd

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Re: [PATCH 1/2] arm64: Add Cortex-X2 CPU part definition

[Anshuman Khandual]

On 1/12/22 4:20 PM, Arnd Bergmann wrote:
> On Wed, Jan 12, 2022 at 10:34 AM Anshuman Khandual
> <anshuman.khandual@arm.com> wrote:
>>
>> Add the CPU Partnumbers for the new Arm designs.
>>
>> Cc: Catalin Marinas <catalin.marinas@arm.com>
>> Cc: Will Deacon <will@kernel.org>
>> Cc: Suzuki Poulose <suzuki.poulose@arm.com>
>> Cc: linux-arm-kernel@lists.infradead.org
>> Cc: linux-kernel@vger.kernel.org
>> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
>> ---
>>  arch/arm64/include/asm/cputype.h | 2 ++
>>  1 file changed, 2 insertions(+)
>>
>> diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h
>> index 19b8441aa8f2..657eeb06c784 100644
>> --- a/arch/arm64/include/asm/cputype.h
>> +++ b/arch/arm64/include/asm/cputype.h
>> @@ -74,6 +74,7 @@
>>  #define ARM_CPU_PART_NEOVERSE_N1       0xD0C
>>  #define ARM_CPU_PART_CORTEX_A77                0xD0D
>>  #define ARM_CPU_PART_CORTEX_A710       0xD47
>> +#define ARM_CPU_PART_CORTEX_X2         0xD48
>>  #define ARM_CPU_PART_NEOVERSE_N2       0xD49
> 
> No objections to the patch, but would it be possible to just add all the missing
> ones here to the degree that they are known already? I don't see any entries for
> Cortex-A34, Cortex-A65AE, Cortex-A78, Cortex-A78C, Cortex-A78AE,
> Neoverse-E1, Neoverse-V1, Cortex-X1, Cortex-X2, Cortex-A510, Cortex-A710
> and Cortex-R82 among the Arm-designed cores that can run Linux, and there
> are probably others that I missed going through the list.

Hi Arnd,

IIUC the part numbers are enumerated here only if there is an errata
applicable for them which needs to be detected at boot. I am not sure
whether all cpu versions that can run Linux, needs to be defined here.
But then I might be missing something.

- Anshuman

> 
>         Arnd
> 

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Re: [PATCH 1/2] arm64: Add Cortex-X2 CPU part definition

[Arnd Bergmann]

On Thu, Jan 13, 2022 at 4:03 AM Anshuman Khandual
<anshuman.khandual@arm.com> wrote:
> On 1/12/22 4:20 PM, Arnd Bergmann wrote:
> > On Wed, Jan 12, 2022 at 10:34 AM Anshuman Khandual <anshuman.khandual@arm.com> wrote:
> >> Add the CPU Partnumbers for the new Arm designs.
> >> @@ -74,6 +74,7 @@
> >>  #define ARM_CPU_PART_NEOVERSE_N1       0xD0C
> >>  #define ARM_CPU_PART_CORTEX_A77                0xD0D
> >>  #define ARM_CPU_PART_CORTEX_A710       0xD47
> >> +#define ARM_CPU_PART_CORTEX_X2         0xD48
> >>  #define ARM_CPU_PART_NEOVERSE_N2       0xD49
> >
> > No objections to the patch, but would it be possible to just add all the missing
> > ones here to the degree that they are known already? I don't see any entries for
> > Cortex-A34, Cortex-A65AE, Cortex-A78, Cortex-A78C, Cortex-A78AE,
> > Neoverse-E1, Neoverse-V1, Cortex-X1, Cortex-X2, Cortex-A510, Cortex-A710
> > and Cortex-R82 among the Arm-designed cores that can run Linux, and there
> > are probably others that I missed going through the list.
>
> Hi Arnd,
>
> IIUC the part numbers are enumerated here only if there is an errata
> applicable for them which needs to be detected at boot. I am not sure
> whether all cpu versions that can run Linux, needs to be defined here.
> But then I might be missing something.

They clearly don't need to be defined here, and for other constants such
as the system registers we may not want to list them all, but I think for
the CPU IDs it makes sense to just list them all here rather than adding
them one at a time, as we tend to need them sooner or later anyway.

It also helps me personally to have a known place to look up the names
by value rather than chasing through reference manuals.

      Arnd

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Re: [PATCH 1/2] arm64: Add Cortex-X2 CPU part definition

[Anshuman Khandual]

On 1/13/22 5:17 PM, Arnd Bergmann wrote:
> On Thu, Jan 13, 2022 at 4:03 AM Anshuman Khandual
> <anshuman.khandual@arm.com> wrote:
>> On 1/12/22 4:20 PM, Arnd Bergmann wrote:
>>> On Wed, Jan 12, 2022 at 10:34 AM Anshuman Khandual <anshuman.khandual@arm.com> wrote:
>>>> Add the CPU Partnumbers for the new Arm designs.
>>>> @@ -74,6 +74,7 @@
>>>>  #define ARM_CPU_PART_NEOVERSE_N1       0xD0C
>>>>  #define ARM_CPU_PART_CORTEX_A77                0xD0D
>>>>  #define ARM_CPU_PART_CORTEX_A710       0xD47
>>>> +#define ARM_CPU_PART_CORTEX_X2         0xD48
>>>>  #define ARM_CPU_PART_NEOVERSE_N2       0xD49
>>>
>>> No objections to the patch, but would it be possible to just add all the missing
>>> ones here to the degree that they are known already? I don't see any entries for
>>> Cortex-A34, Cortex-A65AE, Cortex-A78, Cortex-A78C, Cortex-A78AE,
>>> Neoverse-E1, Neoverse-V1, Cortex-X1, Cortex-X2, Cortex-A510, Cortex-A710
>>> and Cortex-R82 among the Arm-designed cores that can run Linux, and there
>>> are probably others that I missed going through the list.
>>
>> Hi Arnd,
>>
>> IIUC the part numbers are enumerated here only if there is an errata
>> applicable for them which needs to be detected at boot. I am not sure
>> whether all cpu versions that can run Linux, needs to be defined here.
>> But then I might be missing something.
> 
> They clearly don't need to be defined here, and for other constants such
> as the system registers we may not want to list them all, but I think for
> the CPU IDs it makes sense to just list them all here rather than adding
> them one at a time, as we tend to need them sooner or later anyway.
> 
> It also helps me personally to have a known place to look up the names
> by value rather than chasing through reference manuals.

IIUC the purpose here would be a quick CPU ID documentation reference check ?
I will wait for other opinions here and add the remaining in a separate patch
probably.

> 
>       Arnd
> 

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Re: [PATCH 1/2] arm64: Add Cortex-X2 CPU part definition

[Arnd Bergmann]

On Wed, Jan 19, 2022 at 7:44 AM Anshuman Khandual
<anshuman.khandual@arm.com> wrote:
> On 1/13/22 5:17 PM, Arnd Bergmann wrote:
> >
> > It also helps me personally to have a known place to look up the names
> > by value rather than chasing through reference manuals.
>
> IIUC the purpose here would be a quick CPU ID documentation reference check ?
> I will wait for other opinions here and add the remaining in a separate patch
> probably.

The purpose would be to do what is obviously the right thing, and to avoid
more patches getting sent the next time someone needs to add a workaround
for another core that is already known.

If you can't do this without more discussion, then just use your
current version and
let the next person do it.

        Arnd

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Re: [PATCH 1/2] arm64: Add Cortex-X2 CPU part definition

[Mark Rutland]

Hi Arnd,

On Wed, Jan 19, 2022 at 08:44:54AM +0100, Arnd Bergmann wrote:
> On Wed, Jan 19, 2022 at 7:44 AM Anshuman Khandual
> <anshuman.khandual@arm.com> wrote:
> > On 1/13/22 5:17 PM, Arnd Bergmann wrote:
> > >
> > > It also helps me personally to have a known place to look up the names
> > > by value rather than chasing through reference manuals.
> >
> > IIUC the purpose here would be a quick CPU ID documentation reference check ?
> > I will wait for other opinions here and add the remaining in a separate patch
> > probably.
> 
> The purpose would be to do what is obviously the right thing, and to avoid
> more patches getting sent the next time someone needs to add a workaround
> for another core that is already known.

The general policy we've taken is to only add part definitions as and
when they're required (e.g. alongside an errata workaround that needs to
identify the part), since the kernel doesn't otherwise need to know, and
it keeps the errata workaround patches self-contained (and ensures the
MIDR definitions get tested as they're added).

So per usual policy I don't think we should add the other part
definitions here. If and when errata appear that requires us to identify
those parts we can add corresponding MIDR definitions.

> If you can't do this without more discussion, then just use your
> current version and let the next person do it.

As above, for now I think we should leave this as-is, and only add the
Cortex-X2 part definition.

Thanks,
Mark.

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[PATCH 2/2] arm64: errata: Update ARM64_ERRATUM_[2119858|2224489] with Cortex-X2 ranges

[Anshuman Khandual]

Errata ARM64_ERRATUM_[2119858|2224489] also affect some Cortex-X2 ranges as
well. Lets update these errata definition and detection to accommodate all
new Cortex-X2 based cpu MIDR ranges.

Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Cc: Suzuki Poulose <suzuki.poulose@arm.com>
Cc: coresight@lists.linaro.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
---
 arch/arm64/Kconfig             | 12 ++++++------
 arch/arm64/kernel/cpu_errata.c |  2 ++
 2 files changed, 8 insertions(+), 6 deletions(-)

diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index c4207cf9bb17..d8046c832225 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -671,14 +671,14 @@ config ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE
 	bool
 
 config ARM64_ERRATUM_2119858
-	bool "Cortex-A710: 2119858: workaround TRBE overwriting trace data in FILL mode"
+	bool "Cortex-A710/X2: 2119858: workaround TRBE overwriting trace data in FILL mode"
 	default y
 	depends on CORESIGHT_TRBE
 	select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE
 	help
-	  This option adds the workaround for ARM Cortex-A710 erratum 2119858.
+	  This option adds the workaround for ARM Cortex-A710/X2 erratum 2119858.
 
-	  Affected Cortex-A710 cores could overwrite up to 3 cache lines of trace
+	  Affected Cortex-A710/X2 cores could overwrite up to 3 cache lines of trace
 	  data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in
 	  the event of a WRAP event.
 
@@ -761,14 +761,14 @@ config ARM64_ERRATUM_2253138
 	  If unsure, say Y.
 
 config ARM64_ERRATUM_2224489
-	bool "Cortex-A710: 2224489: workaround TRBE writing to address out-of-range"
+	bool "Cortex-A710/X2: 2224489: workaround TRBE writing to address out-of-range"
 	depends on CORESIGHT_TRBE
 	default y
 	select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE
 	help
-	  This option adds the workaround for ARM Cortex-A710 erratum 2224489.
+	  This option adds the workaround for ARM Cortex-A710/X2 erratum 2224489.
 
-	  Affected Cortex-A710 cores might write to an out-of-range address, not reserved
+	  Affected Cortex-A710/X2 cores might write to an out-of-range address, not reserved
 	  for TRBE. Under some conditions, the TRBE might generate a write to the next
 	  virtually addressed page following the last page of the TRBE address space
 	  (i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base.
diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c
index 9e1c1aef9ebd..29cc062a4153 100644
--- a/arch/arm64/kernel/cpu_errata.c
+++ b/arch/arm64/kernel/cpu_errata.c
@@ -347,6 +347,7 @@ static const struct midr_range trbe_overwrite_fill_mode_cpus[] = {
 #endif
 #ifdef CONFIG_ARM64_ERRATUM_2119858
 	MIDR_ALL_VERSIONS(MIDR_CORTEX_A710),
+	MIDR_RANGE(MIDR_CORTEX_X2, 0, 0, 2, 0),
 #endif
 	{},
 };
@@ -371,6 +372,7 @@ static struct midr_range trbe_write_out_of_range_cpus[] = {
 #endif
 #ifdef CONFIG_ARM64_ERRATUM_2224489
 	MIDR_ALL_VERSIONS(MIDR_CORTEX_A710),
+	MIDR_RANGE(MIDR_CORTEX_X2, 0, 0, 2, 0),
 #endif
 	{},
 };
-- 
2.20.1


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Re: [PATCH 2/2] arm64: errata: Update ARM64_ERRATUM_[2119858|2224489] with Cortex-X2 ranges

[Mark Rutland]

Hi Anshuman,

On Wed, Jan 12, 2022 at 03:04:59PM +0530, Anshuman Khandual wrote:
> Errata ARM64_ERRATUM_[2119858|2224489] also affect some Cortex-X2 ranges as
> well. Lets update these errata definition and detection to accommodate all
> new Cortex-X2 based cpu MIDR ranges.
> 
> Cc: Catalin Marinas <catalin.marinas@arm.com>
> Cc: Will Deacon <will@kernel.org>
> Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
> Cc: Suzuki Poulose <suzuki.poulose@arm.com>
> Cc: coresight@lists.linaro.org
> Cc: linux-arm-kernel@lists.infradead.org
> Cc: linux-kernel@vger.kernel.org
> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
> ---
>  arch/arm64/Kconfig             | 12 ++++++------
>  arch/arm64/kernel/cpu_errata.c |  2 ++
>  2 files changed, 8 insertions(+), 6 deletions(-)

I think you've misssed Documentation/arm64/silicon-errata.rst -- for other
common errata we add lines for each affected part, e.g. as we do for
ARM64_ERRATUM_1418040.

Other than that, this looks good to me!

Thanks,
Mark.

> 
> diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
> index c4207cf9bb17..d8046c832225 100644
> --- a/arch/arm64/Kconfig
> +++ b/arch/arm64/Kconfig
> @@ -671,14 +671,14 @@ config ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE
>  	bool
>  
>  config ARM64_ERRATUM_2119858
> -	bool "Cortex-A710: 2119858: workaround TRBE overwriting trace data in FILL mode"
> +	bool "Cortex-A710/X2: 2119858: workaround TRBE overwriting trace data in FILL mode"
>  	default y
>  	depends on CORESIGHT_TRBE
>  	select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE
>  	help
> -	  This option adds the workaround for ARM Cortex-A710 erratum 2119858.
> +	  This option adds the workaround for ARM Cortex-A710/X2 erratum 2119858.
>  
> -	  Affected Cortex-A710 cores could overwrite up to 3 cache lines of trace
> +	  Affected Cortex-A710/X2 cores could overwrite up to 3 cache lines of trace
>  	  data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in
>  	  the event of a WRAP event.
>  
> @@ -761,14 +761,14 @@ config ARM64_ERRATUM_2253138
>  	  If unsure, say Y.
>  
>  config ARM64_ERRATUM_2224489
> -	bool "Cortex-A710: 2224489: workaround TRBE writing to address out-of-range"
> +	bool "Cortex-A710/X2: 2224489: workaround TRBE writing to address out-of-range"
>  	depends on CORESIGHT_TRBE
>  	default y
>  	select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE
>  	help
> -	  This option adds the workaround for ARM Cortex-A710 erratum 2224489.
> +	  This option adds the workaround for ARM Cortex-A710/X2 erratum 2224489.
>  
> -	  Affected Cortex-A710 cores might write to an out-of-range address, not reserved
> +	  Affected Cortex-A710/X2 cores might write to an out-of-range address, not reserved
>  	  for TRBE. Under some conditions, the TRBE might generate a write to the next
>  	  virtually addressed page following the last page of the TRBE address space
>  	  (i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base.
> diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c
> index 9e1c1aef9ebd..29cc062a4153 100644
> --- a/arch/arm64/kernel/cpu_errata.c
> +++ b/arch/arm64/kernel/cpu_errata.c
> @@ -347,6 +347,7 @@ static const struct midr_range trbe_overwrite_fill_mode_cpus[] = {
>  #endif
>  #ifdef CONFIG_ARM64_ERRATUM_2119858
>  	MIDR_ALL_VERSIONS(MIDR_CORTEX_A710),
> +	MIDR_RANGE(MIDR_CORTEX_X2, 0, 0, 2, 0),
>  #endif
>  	{},
>  };
> @@ -371,6 +372,7 @@ static struct midr_range trbe_write_out_of_range_cpus[] = {
>  #endif
>  #ifdef CONFIG_ARM64_ERRATUM_2224489
>  	MIDR_ALL_VERSIONS(MIDR_CORTEX_A710),
> +	MIDR_RANGE(MIDR_CORTEX_X2, 0, 0, 2, 0),
>  #endif
>  	{},
>  };
> -- 
> 2.20.1
> 
> 
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Re: [PATCH 2/2] arm64: errata: Update ARM64_ERRATUM_[2119858|2224489] with Cortex-X2 ranges

[Anshuman Khandual]

On 1/12/22 4:02 PM, Mark Rutland wrote:
> Hi Anshuman,
> 
> On Wed, Jan 12, 2022 at 03:04:59PM +0530, Anshuman Khandual wrote:
>> Errata ARM64_ERRATUM_[2119858|2224489] also affect some Cortex-X2 ranges as
>> well. Lets update these errata definition and detection to accommodate all
>> new Cortex-X2 based cpu MIDR ranges.
>>
>> Cc: Catalin Marinas <catalin.marinas@arm.com>
>> Cc: Will Deacon <will@kernel.org>
>> Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
>> Cc: Suzuki Poulose <suzuki.poulose@arm.com>
>> Cc: coresight@lists.linaro.org
>> Cc: linux-arm-kernel@lists.infradead.org
>> Cc: linux-kernel@vger.kernel.org
>> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
>> ---
>>  arch/arm64/Kconfig             | 12 ++++++------
>>  arch/arm64/kernel/cpu_errata.c |  2 ++
>>  2 files changed, 8 insertions(+), 6 deletions(-)
> 
> I think you've misssed Documentation/arm64/silicon-errata.rst -- for other
> common errata we add lines for each affected part, e.g. as we do for
> ARM64_ERRATUM_1418040.

Sure, will do. I guess Cortex-X2 lines will come just after Cortex-A710
but before Neoverse-N1.

+----------------+-----------------+-----------------+-----------------------------+
| ARM            | Cortex-A710     | #2224489        | ARM64_ERRATUM_2224489       |
+----------------+-----------------+-----------------+-----------------------------+
>
>
+----------------+-----------------+-----------------+-----------------------------+
| ARM            | Neoverse-N1     | #1188873,1418040| ARM64_ERRATUM_1418040       |
+----------------+-----------------+-----------------+-----------------------------+


> 
> Other than that, this looks good to me!
> 
> Thanks,
> Mark.
> 
>>
>> diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
>> index c4207cf9bb17..d8046c832225 100644
>> --- a/arch/arm64/Kconfig
>> +++ b/arch/arm64/Kconfig
>> @@ -671,14 +671,14 @@ config ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE
>>  	bool
>>  
>>  config ARM64_ERRATUM_2119858
>> -	bool "Cortex-A710: 2119858: workaround TRBE overwriting trace data in FILL mode"
>> +	bool "Cortex-A710/X2: 2119858: workaround TRBE overwriting trace data in FILL mode"
>>  	default y
>>  	depends on CORESIGHT_TRBE
>>  	select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE
>>  	help
>> -	  This option adds the workaround for ARM Cortex-A710 erratum 2119858.
>> +	  This option adds the workaround for ARM Cortex-A710/X2 erratum 2119858.
>>  
>> -	  Affected Cortex-A710 cores could overwrite up to 3 cache lines of trace
>> +	  Affected Cortex-A710/X2 cores could overwrite up to 3 cache lines of trace
>>  	  data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in
>>  	  the event of a WRAP event.
>>  
>> @@ -761,14 +761,14 @@ config ARM64_ERRATUM_2253138
>>  	  If unsure, say Y.
>>  
>>  config ARM64_ERRATUM_2224489
>> -	bool "Cortex-A710: 2224489: workaround TRBE writing to address out-of-range"
>> +	bool "Cortex-A710/X2: 2224489: workaround TRBE writing to address out-of-range"
>>  	depends on CORESIGHT_TRBE
>>  	default y
>>  	select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE
>>  	help
>> -	  This option adds the workaround for ARM Cortex-A710 erratum 2224489.
>> +	  This option adds the workaround for ARM Cortex-A710/X2 erratum 2224489.
>>  
>> -	  Affected Cortex-A710 cores might write to an out-of-range address, not reserved
>> +	  Affected Cortex-A710/X2 cores might write to an out-of-range address, not reserved
>>  	  for TRBE. Under some conditions, the TRBE might generate a write to the next
>>  	  virtually addressed page following the last page of the TRBE address space
>>  	  (i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base.
>> diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c
>> index 9e1c1aef9ebd..29cc062a4153 100644
>> --- a/arch/arm64/kernel/cpu_errata.c
>> +++ b/arch/arm64/kernel/cpu_errata.c
>> @@ -347,6 +347,7 @@ static const struct midr_range trbe_overwrite_fill_mode_cpus[] = {
>>  #endif
>>  #ifdef CONFIG_ARM64_ERRATUM_2119858
>>  	MIDR_ALL_VERSIONS(MIDR_CORTEX_A710),
>> +	MIDR_RANGE(MIDR_CORTEX_X2, 0, 0, 2, 0),
>>  #endif
>>  	{},
>>  };
>> @@ -371,6 +372,7 @@ static struct midr_range trbe_write_out_of_range_cpus[] = {
>>  #endif
>>  #ifdef CONFIG_ARM64_ERRATUM_2224489
>>  	MIDR_ALL_VERSIONS(MIDR_CORTEX_A710),
>> +	MIDR_RANGE(MIDR_CORTEX_X2, 0, 0, 2, 0),
>>  #endif
>>  	{},
>>  };
>> -- 
>> 2.20.1
>>
>>
>> _______________________________________________
>> linux-arm-kernel mailing list
>> linux-arm-kernel@lists.infradead.org
>> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

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Re: [PATCH 2/2] arm64: errata: Update ARM64_ERRATUM_[2119858|2224489] with Cortex-X2 ranges

[Mark Rutland]

On Wed, Jan 12, 2022 at 04:36:07PM +0530, Anshuman Khandual wrote:
> 
> 
> On 1/12/22 4:02 PM, Mark Rutland wrote:
> > Hi Anshuman,
> > 
> > On Wed, Jan 12, 2022 at 03:04:59PM +0530, Anshuman Khandual wrote:
> >> Errata ARM64_ERRATUM_[2119858|2224489] also affect some Cortex-X2 ranges as
> >> well. Lets update these errata definition and detection to accommodate all
> >> new Cortex-X2 based cpu MIDR ranges.
> >>
> >> Cc: Catalin Marinas <catalin.marinas@arm.com>
> >> Cc: Will Deacon <will@kernel.org>
> >> Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
> >> Cc: Suzuki Poulose <suzuki.poulose@arm.com>
> >> Cc: coresight@lists.linaro.org
> >> Cc: linux-arm-kernel@lists.infradead.org
> >> Cc: linux-kernel@vger.kernel.org
> >> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
> >> ---
> >>  arch/arm64/Kconfig             | 12 ++++++------
> >>  arch/arm64/kernel/cpu_errata.c |  2 ++
> >>  2 files changed, 8 insertions(+), 6 deletions(-)
> > 
> > I think you've misssed Documentation/arm64/silicon-errata.rst -- for other
> > common errata we add lines for each affected part, e.g. as we do for
> > ARM64_ERRATUM_1418040.
> 
> Sure, will do. I guess Cortex-X2 lines will come just after Cortex-A710
> but before Neoverse-N1.
> 
> +----------------+-----------------+-----------------+-----------------------------+
> | ARM            | Cortex-A710     | #2224489        | ARM64_ERRATUM_2224489       |
> +----------------+-----------------+-----------------+-----------------------------+
> >
> >
> +----------------+-----------------+-----------------+-----------------------------+
> | ARM            | Neoverse-N1     | #1188873,1418040| ARM64_ERRATUM_1418040       |
> +----------------+-----------------+-----------------+-----------------------------+

That sounds right to me, yes.

Thanks,
Mark.

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