From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 17058C433F5 for ; Sun, 6 Feb 2022 12:26:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-ID:Date:From:Cc:To :Subject:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=yj2OWXrRNYZVPDwiJ+y5+LsBLTkoPhLUkyVbuk11MZ4=; b=QKGZid+XnuHw6F fSJ2QflNdBRUxtIa8OjRn8pSdR7UkNvL/oJLWiJ3qoOOsXDQaS8EAcSSjBpHUkGZilSTHW1/J4FfZ o49PnfUBvWqWLbOGNNnbGpKZODRHZUjnUABPkG+aJRkRE67l6trGz7X15/bITWmkI5AF5FONgM7X/ sZwd9VUX37/qnFp8PmXPIBsqdi2I2AbOLYsFLVv6yAwmx6zH+lJxWTNWhHfoBlhjSwkEEILWxMVgj 13J1fXmSoL00Q/3Qq1Z4S338sXUfSmfQvU7iSt0wNJ80tVlAeBA1YSPuV2Tf5ZmakLpWjMAJMSWbh vTE08vw3A4RCsHF1q73A==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nGgbd-008AFn-Q9; Sun, 06 Feb 2022 12:25:25 +0000 Received: from dfw.source.kernel.org ([2604:1380:4641:c500::1]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nGgba-008AFT-Ct for linux-arm-kernel@lists.infradead.org; Sun, 06 Feb 2022 12:25:24 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 8D66660FA9; Sun, 6 Feb 2022 12:25:21 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 6F57DC340E9; Sun, 6 Feb 2022 12:25:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linuxfoundation.org; s=korg; t=1644150321; bh=PTgLj7ZDX8S2ECgl0d9lRSXQENmleTOkZ73Q+Uw3el0=; h=Subject:To:Cc:From:Date:From; b=hlsBmA0AHNIntHQYuvMyFsFEDGbfEt11wGKw31VDC0t7fv1fiREJIj5LqTsTNjRjl jizZCDfIIZUv3acn4rcvuECdEG9W2djaFgjyeFiWdpNUvowlBinlaiUOcv9ii7WFAP So1MCr1ctEUEnOFKCSaslXAcFKp3hXPrlu9/xFA8= Subject: Patch "arm64: Add Cortex-A510 CPU part definition" has been added to the 5.16-stable tree To: anshuman.khandual@arm.com, catalin.marinas@arm.com, gregkh@linuxfoundation.org, linux-arm-kernel@lists.infradead.org, mathieu.poirier@linaro.org, suzuki.poulose@arm.com, will@kernel.org Cc: From: Date: Sun, 06 Feb 2022 13:25:18 +0100 Message-ID: <164415031815279@kroah.com> MIME-Version: 1.0 X-stable: commit X-Patchwork-Hint: ignore X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220206_042522_576943_80E43FCE X-CRM114-Status: GOOD ( 13.89 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This is a note to let you know that I've just added the patch titled arm64: Add Cortex-A510 CPU part definition to the 5.16-stable tree which can be found at: http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary The filename of the patch is: arm64-add-cortex-a510-cpu-part-definition.patch and it can be found in the queue-5.16 subdirectory. If you, or anyone else, feels it should not be added to the stable tree, please let know about it. >From 53960faf2b731dd2f9ed6e1334634b8ba6286850 Mon Sep 17 00:00:00 2001 From: Anshuman Khandual Date: Tue, 25 Jan 2022 19:50:31 +0530 Subject: arm64: Add Cortex-A510 CPU part definition From: Anshuman Khandual commit 53960faf2b731dd2f9ed6e1334634b8ba6286850 upstream. Add the CPU Partnumbers for the new Arm designs. Cc: Catalin Marinas Cc: Will Deacon Cc: Suzuki Poulose Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Reviewed-by: Suzuki K Poulose Acked-by: Catalin Marinas Signed-off-by: Anshuman Khandual Link: https://lore.kernel.org/r/1643120437-14352-2-git-send-email-anshuman.khandual@arm.com Signed-off-by: Mathieu Poirier Signed-off-by: Greg Kroah-Hartman --- arch/arm64/include/asm/cputype.h | 2 ++ 1 file changed, 2 insertions(+) --- a/arch/arm64/include/asm/cputype.h +++ b/arch/arm64/include/asm/cputype.h @@ -73,6 +73,7 @@ #define ARM_CPU_PART_CORTEX_A76 0xD0B #define ARM_CPU_PART_NEOVERSE_N1 0xD0C #define ARM_CPU_PART_CORTEX_A77 0xD0D +#define ARM_CPU_PART_CORTEX_A510 0xD46 #define ARM_CPU_PART_CORTEX_A710 0xD47 #define ARM_CPU_PART_NEOVERSE_N2 0xD49 @@ -115,6 +116,7 @@ #define MIDR_CORTEX_A76 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A76) #define MIDR_NEOVERSE_N1 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N1) #define MIDR_CORTEX_A77 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A77) +#define MIDR_CORTEX_A510 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A510) #define MIDR_CORTEX_A710 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A710) #define MIDR_NEOVERSE_N2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N2) #define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX) Patches currently in stable-queue which might be from anshuman.khandual@arm.com are queue-5.16/arm64-add-cortex-a510-cpu-part-definition.patch queue-5.16/mm-debug_vm_pgtable-remove-pte-entry-from-the-page-table.patch _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel