* [PATCH v4 0/7] Add R8A7743/SK-RZG1M board support
@ 2016-10-21 20:39 Sergei Shtylyov
2016-10-21 20:40 ` [PATCH v4 1/7] ARM: dts: r8a7743: initial SoC device tree Sergei Shtylyov
` (7 more replies)
0 siblings, 8 replies; 12+ messages in thread
From: Sergei Shtylyov @ 2016-10-21 20:39 UTC (permalink / raw)
To: linux-arm-kernel
Hello.
Here's the set of 8 patches against Simon Horman's 'renesas.git' repo's
'renesas-devel-20161021-v4.9-rc1' tag. I'm adding the device tree support for
the R8A7743-based SK-RZG1M board. The SoC is close to R8A7791 and the board
seems identical to the R8A7791/Porter board. The device tree patches depend on
the R8A7743 CPG/MSSR driver series just posted in order to compile and work.
Already merged patches from this series won't be re-posted.
[1/7] ARM: dts: r8a7743: initial SoC device tree
[2/7] ARM: dts: r8a7743: add SYS-DMAC support
[3/7] ARM: dts: r8a7743: add [H]SCIF{A|B} support
[4/7] ARM: dts: r8a7743: add Ether support
[5/7] ARM: dts: r8a7743: add IRQC support
[6/7] ARM: dts: sk-rzg1m: initial device tree
[7/7] ARM: dts: sk-rzg1m: add Ether support
WBR, Sergei
^ permalink raw reply [flat|nested] 12+ messages in thread* [PATCH v4 1/7] ARM: dts: r8a7743: initial SoC device tree 2016-10-21 20:39 [PATCH v4 0/7] Add R8A7743/SK-RZG1M board support Sergei Shtylyov @ 2016-10-21 20:40 ` Sergei Shtylyov 2016-10-21 20:41 ` [PATCH v4 2/7] ARM: dts: r8a7743: add SYS-DMAC support Sergei Shtylyov ` (6 subsequent siblings) 7 siblings, 0 replies; 12+ messages in thread From: Sergei Shtylyov @ 2016-10-21 20:40 UTC (permalink / raw) To: linux-arm-kernel The initial R8A7743 SoC device tree including CPU0, GIC, timer, SYSC, CPG, and the required clock descriptions. Based on the original (and large) patch by Dmitry Shifrin <dmitry.shifrin@cogentembedded.com>. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> --- Changes in version 4: - removed the CPU1 node, updated the patch description accordingly; - reformatted the "interrupts" props of the GIC/timer device nodes; - added Geert's tag. Changes in version 3: - changed the R8A7743 clock header #include; - replaced the multiple clock nodes with the single CPG node, updated the "clocks" property in the CPU0 node, updated the patch description. Changes in version 2: - added the IRQC and Ether clocks. arch/arm/boot/dts/r8a7743.dtsi | 115 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 115 insertions(+) Index: renesas/arch/arm/boot/dts/r8a7743.dtsi =================================================================== --- /dev/null +++ renesas/arch/arm/boot/dts/r8a7743.dtsi @@ -0,0 +1,115 @@ +/* + * Device Tree Source for the r8a7743 SoC + * + * Copyright (C) 2016 Cogent Embedded Inc. + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/clock/r8a7743-cpg-mssr.h> +#include <dt-bindings/power/r8a7743-sysc.h> + +/ { + compatible = "renesas,r8a7743"; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu at 0 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0>; + clock-frequency = <1500000000>; + clocks = <&cpg CPG_CORE R8A7743_CLK_Z>; + power-domains = <&sysc R8A7743_PD_CA15_CPU0>; + next-level-cache = <&L2_CA15>; + }; + + L2_CA15: cache-controller at 0 { + compatible = "cache"; + reg = <0>; + cache-unified; + cache-level = <2>; + power-domains = <&sysc R8A7743_PD_CA15_SCU>; + }; + }; + + soc { + compatible = "simple-bus"; + interrupt-parent = <&gic>; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gic: interrupt-controller at f1001000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0 0xf1001000 0 0x1000>, + <0 0xf1002000 0 0x1000>, + <0 0xf1004000 0 0x2000>, + <0 0xf1006000 0 0x2000>; + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | + IRQ_TYPE_LEVEL_HIGH)>; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | + IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | + IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | + IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | + IRQ_TYPE_LEVEL_LOW)>; + }; + + cpg: clock-controller at e6150000 { + compatible = "renesas,r8a7743-cpg-mssr"; + reg = <0 0xe6150000 0 0x1000>; + clocks = <&extal_clk>, <&usb_extal_clk>; + clock-names = "extal", "usb_extal"; + #clock-cells = <2>; + #power-domain-cells = <0>; + }; + + sysc: system-controller at e6180000 { + compatible = "renesas,r8a7743-sysc"; + reg = <0 0xe6180000 0 0x0200>; + #power-domain-cells = <1>; + }; + }; + + /* External root clock */ + extal_clk: extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overriden by the board. */ + clock-frequency = <0>; + }; + + /* External USB clock - can be overridden by the board */ + usb_extal_clk: usb_extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <48000000>; + }; + + /* External SCIF clock */ + scif_clk: scif { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + }; +}; ^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH v4 2/7] ARM: dts: r8a7743: add SYS-DMAC support 2016-10-21 20:39 [PATCH v4 0/7] Add R8A7743/SK-RZG1M board support Sergei Shtylyov 2016-10-21 20:40 ` [PATCH v4 1/7] ARM: dts: r8a7743: initial SoC device tree Sergei Shtylyov @ 2016-10-21 20:41 ` Sergei Shtylyov 2016-10-21 20:42 ` [PATCH v4 3/7] ARM: dts: r8a7743: add [H]SCIF{|A|B} support Sergei Shtylyov ` (5 subsequent siblings) 7 siblings, 0 replies; 12+ messages in thread From: Sergei Shtylyov @ 2016-10-21 20:41 UTC (permalink / raw) To: linux-arm-kernel Describe SYS-DMAC0/1 in the R8A7743 device tree. Based on the original (and large) patch by Dmitry Shifrin <dmitry.shifrin@cogentembedded.com>. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> --- Changes in version 4: - refreshed the patch. Changes in version 3: - resolved a reject; - updated the "clocks" properties for the CPG/MSSR driver. Changes in version 2: - added Geert's tag. arch/arm/boot/dts/r8a7743.dtsi | 64 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 64 insertions(+) Index: renesas/arch/arm/boot/dts/r8a7743.dtsi =================================================================== --- renesas.orig/arch/arm/boot/dts/r8a7743.dtsi +++ renesas/arch/arm/boot/dts/r8a7743.dtsi @@ -88,6 +88,70 @@ reg = <0 0xe6180000 0 0x0200>; #power-domain-cells = <1>; }; + + dmac0: dma-controller at e6700000 { + compatible = "renesas,dmac-r8a7743", + "renesas,rcar-dmac"; + reg = <0 0xe6700000 0 0x20000>; + interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14"; + clocks = <&cpg CPG_MOD 219>; + clock-names = "fck"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + #dma-cells = <1>; + dma-channels = <15>; + }; + + dmac1: dma-controller at e6720000 { + compatible = "renesas,dmac-r8a7743", + "renesas,rcar-dmac"; + reg = <0 0xe6720000 0 0x20000>; + interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14"; + clocks = <&cpg CPG_MOD 218>; + clock-names = "fck"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + #dma-cells = <1>; + dma-channels = <15>; + }; }; /* External root clock */ ^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH v4 3/7] ARM: dts: r8a7743: add [H]SCIF{|A|B} support 2016-10-21 20:39 [PATCH v4 0/7] Add R8A7743/SK-RZG1M board support Sergei Shtylyov 2016-10-21 20:40 ` [PATCH v4 1/7] ARM: dts: r8a7743: initial SoC device tree Sergei Shtylyov 2016-10-21 20:41 ` [PATCH v4 2/7] ARM: dts: r8a7743: add SYS-DMAC support Sergei Shtylyov @ 2016-10-21 20:42 ` Sergei Shtylyov 2016-10-21 20:45 ` [PATCH v4 4/7] ARM: dts: r8a7743: add Ether support Sergei Shtylyov ` (4 subsequent siblings) 7 siblings, 0 replies; 12+ messages in thread From: Sergei Shtylyov @ 2016-10-21 20:42 UTC (permalink / raw) To: linux-arm-kernel Describe [H]SCIF{|A|B} ports in the R8A7743 device tree. Based on the original (and large) patch by Dmitry Shifrin <dmitry.shifrin@cogentembedded.com>. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> --- Changes in version 4: - corrected RBNF in the patch description/subject; - used the R-Car gen2 bindings instead of the RZ/G family ones; - refreshed the patch; - added Geert's tag. Changes in version 3: - resolved a reject; - updated the "clocks" properties for the CPG/MSSR driver; - renamed the patch. Changes in version 2: - used the new RZ/G family "compatible" prop values, reformatting where needed; - fixed the size cells of the SCIFB device nodes' "reg" properties; - changed the size cells of the "reg" properties to hexadecimal; - indented the SCIFA1 device node's closing brace correctly - adjusted the patch description, renamed the patch. arch/arm/boot/dts/r8a7743.dtsi | 261 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 261 insertions(+) Index: renesas/arch/arm/boot/dts/r8a7743.dtsi =================================================================== --- renesas.orig/arch/arm/boot/dts/r8a7743.dtsi +++ renesas/arch/arm/boot/dts/r8a7743.dtsi @@ -152,6 +152,267 @@ #dma-cells = <1>; dma-channels = <15>; }; + + scifa0: serial at e6c40000 { + compatible = "renesas,scifa-r8a7743", + "renesas,rcar-gen2-scifa", "renesas,scifa"; + reg = <0 0xe6c40000 0 0x40>; + interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 204>; + clock-names = "fck"; + dmas = <&dmac0 0x21>, <&dmac0 0x22>, + <&dmac1 0x21>, <&dmac1 0x22>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + status = "disabled"; + }; + + scifa1: serial at e6c50000 { + compatible = "renesas,scifa-r8a7743", + "renesas,rcar-gen2-scifa", "renesas,scifa"; + reg = <0 0xe6c50000 0 0x40>; + interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 203>; + clock-names = "fck"; + dmas = <&dmac0 0x25>, <&dmac0 0x26>, + <&dmac1 0x25>, <&dmac1 0x26>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + status = "disabled"; + }; + + scifa2: serial at e6c60000 { + compatible = "renesas,scifa-r8a7743", + "renesas,rcar-gen2-scifa", "renesas,scifa"; + reg = <0 0xe6c60000 0 0x40>; + interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 202>; + clock-names = "fck"; + dmas = <&dmac0 0x27>, <&dmac0 0x28>, + <&dmac1 0x27>, <&dmac1 0x28>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + status = "disabled"; + }; + + scifa3: serial at e6c70000 { + compatible = "renesas,scifa-r8a7743", + "renesas,rcar-gen2-scifa", "renesas,scifa"; + reg = <0 0xe6c70000 0 0x40>; + interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 1106>; + clock-names = "fck"; + dmas = <&dmac0 0x1b>, <&dmac0 0x1c>, + <&dmac1 0x1b>, <&dmac1 0x1c>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + status = "disabled"; + }; + + scifa4: serial at e6c78000 { + compatible = "renesas,scifa-r8a7743", + "renesas,rcar-gen2-scifa", "renesas,scifa"; + reg = <0 0xe6c78000 0 0x40>; + interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 1107>; + clock-names = "fck"; + dmas = <&dmac0 0x1f>, <&dmac0 0x20>, + <&dmac1 0x1f>, <&dmac1 0x20>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + status = "disabled"; + }; + + scifa5: serial at e6c80000 { + compatible = "renesas,scifa-r8a7743", + "renesas,rcar-gen2-scifa", "renesas,scifa"; + reg = <0 0xe6c80000 0 0x40>; + interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 1108>; + clock-names = "fck"; + dmas = <&dmac0 0x23>, <&dmac0 0x24>, + <&dmac1 0x23>, <&dmac1 0x24>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + status = "disabled"; + }; + + scifb0: serial at e6c20000 { + compatible = "renesas,scifb-r8a7743", + "renesas,rcar-gen2-scifb", "renesas,scifb"; + reg = <0 0xe6c20000 0 0x100>; + interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 206>; + clock-names = "fck"; + dmas = <&dmac0 0x3d>, <&dmac0 0x3e>, + <&dmac1 0x3d>, <&dmac1 0x3e>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + status = "disabled"; + }; + + scifb1: serial at e6c30000 { + compatible = "renesas,scifb-r8a7743", + "renesas,rcar-gen2-scifb", "renesas,scifb"; + reg = <0 0xe6c30000 0 0x100>; + interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 207>; + clock-names = "fck"; + dmas = <&dmac0 0x19>, <&dmac0 0x1a>, + <&dmac1 0x19>, <&dmac1 0x1a>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + status = "disabled"; + }; + + scifb2: serial at e6ce0000 { + compatible = "renesas,scifb-r8a7743", + "renesas,rcar-gen2-scifb", "renesas,scifb"; + reg = <0 0xe6ce0000 0 0x100>; + interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 216>; + clock-names = "fck"; + dmas = <&dmac0 0x1d>, <&dmac0 0x1e>, + <&dmac1 0x1d>, <&dmac1 0x1e>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + status = "disabled"; + }; + + scif0: serial at e6e60000 { + compatible = "renesas,scif-r8a7743", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6e60000 0 0x40>; + interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 721>, + <&cpg CPG_CORE R8A7743_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x29>, <&dmac0 0x2a>, + <&dmac1 0x29>, <&dmac1 0x2a>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + status = "disabled"; + }; + + scif1: serial at e6e68000 { + compatible = "renesas,scif-r8a7743", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6e68000 0 0x40>; + interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 720>, + <&cpg CPG_CORE R8A7743_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x2d>, <&dmac0 0x2e>, + <&dmac1 0x2d>, <&dmac1 0x2e>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + status = "disabled"; + }; + + scif2: serial at e6e58000 { + compatible = "renesas,scif-r8a7743", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6e58000 0 0x40>; + interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 719>, + <&cpg CPG_CORE R8A7743_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x2b>, <&dmac0 0x2c>, + <&dmac1 0x2b>, <&dmac1 0x2c>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + status = "disabled"; + }; + + scif3: serial at e6ea8000 { + compatible = "renesas,scif-r8a7743", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6ea8000 0 0x40>; + interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 718>, + <&cpg CPG_CORE R8A7743_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x2f>, <&dmac0 0x30>, + <&dmac1 0x2f>, <&dmac1 0x30>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + status = "disabled"; + }; + + scif4: serial at e6ee0000 { + compatible = "renesas,scif-r8a7743", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6ee0000 0 0x40>; + interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 715>, + <&cpg CPG_CORE R8A7743_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0xfb>, <&dmac0 0xfc>, + <&dmac1 0xfb>, <&dmac1 0xfc>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + status = "disabled"; + }; + + scif5: serial at e6ee8000 { + compatible = "renesas,scif-r8a7743", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6ee8000 0 0x40>; + interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 714>, + <&cpg CPG_CORE R8A7743_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0xfd>, <&dmac0 0xfe>, + <&dmac1 0xfd>, <&dmac1 0xfe>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + status = "disabled"; + }; + + hscif0: serial at e62c0000 { + compatible = "renesas,hscif-r8a7743", + "renesas,rcar-gen2-hscif", "renesas,hscif"; + reg = <0 0xe62c0000 0 0x60>; + interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 717>, + <&cpg CPG_CORE R8A7743_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x39>, <&dmac0 0x3a>, + <&dmac1 0x39>, <&dmac1 0x3a>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + status = "disabled"; + }; + + hscif1: serial at e62c8000 { + compatible = "renesas,hscif-r8a7743", + "renesas,rcar-gen2-hscif", "renesas,hscif"; + reg = <0 0xe62c8000 0 0x60>; + interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 716>, + <&cpg CPG_CORE R8A7743_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x4d>, <&dmac0 0x4e>, + <&dmac1 0x4d>, <&dmac1 0x4e>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + status = "disabled"; + }; + + hscif2: serial at e62d0000 { + compatible = "renesas,hscif-r8a7743", + "renesas,rcar-gen2-hscif", "renesas,hscif"; + reg = <0 0xe62d0000 0 0x60>; + interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 713>, + <&cpg CPG_CORE R8A7743_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x3b>, <&dmac0 0x3c>, + <&dmac1 0x3b>, <&dmac1 0x3c>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + status = "disabled"; + }; }; /* External root clock */ ^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH v4 4/7] ARM: dts: r8a7743: add Ether support 2016-10-21 20:39 [PATCH v4 0/7] Add R8A7743/SK-RZG1M board support Sergei Shtylyov ` (2 preceding siblings ...) 2016-10-21 20:42 ` [PATCH v4 3/7] ARM: dts: r8a7743: add [H]SCIF{|A|B} support Sergei Shtylyov @ 2016-10-21 20:45 ` Sergei Shtylyov 2016-10-21 20:46 ` [PATCH v4 5/7] ARM: dts: r8a7743: add IRQC support Sergei Shtylyov ` (3 subsequent siblings) 7 siblings, 0 replies; 12+ messages in thread From: Sergei Shtylyov @ 2016-10-21 20:45 UTC (permalink / raw) To: linux-arm-kernel Define the generic R8A7743 part of the Ether device node. Based on the original (and large) patch by Dmitry Shifrin <dmitry.shifrin@cogentembedded.com>. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> --- Changes in version 4: - refreshed the patch; - added Geert's tag. Changes in version 3: - resolved a reject; - updated the "clocks" property for the CPG/MSSR driver. Changes in version 2: - new patch. arch/arm/boot/dts/r8a7743.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) Index: renesas/arch/arm/boot/dts/r8a7743.dtsi =================================================================== --- renesas.orig/arch/arm/boot/dts/r8a7743.dtsi +++ renesas/arch/arm/boot/dts/r8a7743.dtsi @@ -413,6 +413,18 @@ power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; status = "disabled"; }; + + ether: ethernet at ee700000 { + compatible = "renesas,ether-r8a7743"; + reg = <0 0xee700000 0 0x400>; + interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 813>; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + phy-mode = "rmii"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; }; /* External root clock */ ^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH v4 5/7] ARM: dts: r8a7743: add IRQC support 2016-10-21 20:39 [PATCH v4 0/7] Add R8A7743/SK-RZG1M board support Sergei Shtylyov ` (3 preceding siblings ...) 2016-10-21 20:45 ` [PATCH v4 4/7] ARM: dts: r8a7743: add Ether support Sergei Shtylyov @ 2016-10-21 20:46 ` Sergei Shtylyov 2016-10-21 20:47 ` [PATCH v4 6/7] ARM: dts: sk-rzg1m: initial device tree Sergei Shtylyov ` (2 subsequent siblings) 7 siblings, 0 replies; 12+ messages in thread From: Sergei Shtylyov @ 2016-10-21 20:46 UTC (permalink / raw) To: linux-arm-kernel Describe the IRQC interrupt controller in the R8A7743 device tree. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> --- Changes in version 4: - refreshed the patch; - added Geert's tag. Changes in version 3: - updated the "clocks" property for the CPG/MSSR driver. Changes in version 2: - new patch. arch/arm/boot/dts/r8a7743.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) Index: renesas/arch/arm/boot/dts/r8a7743.dtsi =================================================================== --- renesas.orig/arch/arm/boot/dts/r8a7743.dtsi +++ renesas/arch/arm/boot/dts/r8a7743.dtsi @@ -62,6 +62,25 @@ IRQ_TYPE_LEVEL_HIGH)>; }; + irqc: interrupt-controller at e61c0000 { + compatible = "renesas,irqc-r8a7743", "renesas,irqc"; + #interrupt-cells = <2>; + interrupt-controller; + reg = <0 0xe61c0000 0 0x200>; + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 407>; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + }; + timer { compatible = "arm,armv7-timer"; interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | ^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH v4 6/7] ARM: dts: sk-rzg1m: initial device tree 2016-10-21 20:39 [PATCH v4 0/7] Add R8A7743/SK-RZG1M board support Sergei Shtylyov ` (4 preceding siblings ...) 2016-10-21 20:46 ` [PATCH v4 5/7] ARM: dts: r8a7743: add IRQC support Sergei Shtylyov @ 2016-10-21 20:47 ` Sergei Shtylyov 2016-10-21 20:48 ` [PATCH v4 7/7] ARM: dts: sk-rzg1m: add Ether support Sergei Shtylyov 2016-10-26 12:08 ` [PATCH v4 0/7] Add R8A7743/SK-RZG1M board support Geert Uytterhoeven 7 siblings, 0 replies; 12+ messages in thread From: Sergei Shtylyov @ 2016-10-21 20:47 UTC (permalink / raw) To: linux-arm-kernel Add the initial device tree for the R8A7743 SoC based SK-RZG1M board. The board has one debug serial port (SCIF0); include support for it, so that the serial console can work. Based on the original (and large) patch by Dmitry Shifrin <dmitry.shifrin@cogentembedded.com>. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> --- Changes in version 4: - refreshed the patch. Changes in version 3: - added Geert's tag. arch/arm/boot/dts/Makefile | 1 arch/arm/boot/dts/r8a7743-sk-rzg1m.dts | 44 +++++++++++++++++++++++++++++++++ 2 files changed, 45 insertions(+) Index: renesas/arch/arm/boot/dts/Makefile =================================================================== --- renesas.orig/arch/arm/boot/dts/Makefile +++ renesas/arch/arm/boot/dts/Makefile @@ -677,6 +677,7 @@ dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += \ r7s72100-rskrza1.dtb \ r8a73a4-ape6evm.dtb \ r8a7740-armadillo800eva.dtb \ + r8a7743-sk-rzg1m.dtb \ r8a7778-bockw.dtb \ r8a7779-marzen.dtb \ r8a7790-lager.dtb \ Index: renesas/arch/arm/boot/dts/r8a7743-sk-rzg1m.dts =================================================================== --- /dev/null +++ renesas/arch/arm/boot/dts/r8a7743-sk-rzg1m.dts @@ -0,0 +1,44 @@ +/* + * Device Tree Source for the SK-RZG1M board + * + * Copyright (C) 2016 Cogent Embedded, Inc. + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +/dts-v1/; +#include "r8a7743.dtsi" + +/ { + model = "SK-RZG1M"; + compatible = "renesas,sk-rzg1m", "renesas,r8a7743"; + + aliases { + serial0 = &scif0; + }; + + chosen { + bootargs = "ignore_loglevel"; + stdout-path = "serial0:115200n8"; + }; + + memory at 40000000 { + device_type = "memory"; + reg = <0 0x40000000 0 0x40000000>; + }; + + memory at 200000000 { + device_type = "memory"; + reg = <2 0x00000000 0 0x40000000>; + }; +}; + +&extal_clk { + clock-frequency = <20000000>; +}; + +&scif0 { + status = "okay"; +}; ^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH v4 7/7] ARM: dts: sk-rzg1m: add Ether support 2016-10-21 20:39 [PATCH v4 0/7] Add R8A7743/SK-RZG1M board support Sergei Shtylyov ` (5 preceding siblings ...) 2016-10-21 20:47 ` [PATCH v4 6/7] ARM: dts: sk-rzg1m: initial device tree Sergei Shtylyov @ 2016-10-21 20:48 ` Sergei Shtylyov 2016-10-26 12:08 ` [PATCH v4 0/7] Add R8A7743/SK-RZG1M board support Geert Uytterhoeven 7 siblings, 0 replies; 12+ messages in thread From: Sergei Shtylyov @ 2016-10-21 20:48 UTC (permalink / raw) To: linux-arm-kernel Define the SK-RZG1M board dependent part of the Ether device node. Enable DHCP and NFS root for the kernel booting. Based on the original (and large) patch by Dmitry Shifrin <dmitry.shifrin@cogentembedded.com>. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> --- Changes in version 4: - added Geert's tag. Changes in version 2: - new patch. arch/arm/boot/dts/r8a7743-sk-rzg1m.dts | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) Index: renesas/arch/arm/boot/dts/r8a7743-sk-rzg1m.dts =================================================================== --- renesas.orig/arch/arm/boot/dts/r8a7743-sk-rzg1m.dts +++ renesas/arch/arm/boot/dts/r8a7743-sk-rzg1m.dts @@ -20,7 +20,7 @@ }; chosen { - bootargs = "ignore_loglevel"; + bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp"; stdout-path = "serial0:115200n8"; }; @@ -42,3 +42,16 @@ &scif0 { status = "okay"; }; + +ðer { + phy-handle = <&phy1>; + renesas,ether-link-active-low; + status = "okay"; + + phy1: ethernet-phy at 1 { + reg = <1>; + interrupt-parent = <&irqc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + micrel,led-mode = <1>; + }; +}; ^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH v4 0/7] Add R8A7743/SK-RZG1M board support 2016-10-21 20:39 [PATCH v4 0/7] Add R8A7743/SK-RZG1M board support Sergei Shtylyov ` (6 preceding siblings ...) 2016-10-21 20:48 ` [PATCH v4 7/7] ARM: dts: sk-rzg1m: add Ether support Sergei Shtylyov @ 2016-10-26 12:08 ` Geert Uytterhoeven 2016-10-26 13:23 ` Sergei Shtylyov 7 siblings, 1 reply; 12+ messages in thread From: Geert Uytterhoeven @ 2016-10-26 12:08 UTC (permalink / raw) To: linux-arm-kernel Hi Sergei, On Fri, Oct 21, 2016 at 10:39 PM, Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> wrote: > Here's the set of 8 patches against Simon Horman's 'renesas.git' repo's > 'renesas-devel-20161021-v4.9-rc1' tag. I'm adding the device tree support for > the R8A7743-based SK-RZG1M board. The SoC is close to R8A7791 and the board > seems identical to the R8A7791/Porter board. The device tree patches depend on > the R8A7743 CPG/MSSR driver series just posted in order to compile and work. They depend only on "[PATCH v3 1/2] ARM: shmobile: r8a7743: add CPG clock index macros" of that series, right? "[PATCH v3 2/2] clk: renesas: cpg-mssr: add R8A7743 support" is not needed, and introduces an additional dependency on "[PATCH 1/3] clk: renesas: cpg-mssr: add common R-Car Gen2 support". Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds ^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH v4 0/7] Add R8A7743/SK-RZG1M board support 2016-10-26 12:08 ` [PATCH v4 0/7] Add R8A7743/SK-RZG1M board support Geert Uytterhoeven @ 2016-10-26 13:23 ` Sergei Shtylyov 2016-10-26 13:27 ` Geert Uytterhoeven 0 siblings, 1 reply; 12+ messages in thread From: Sergei Shtylyov @ 2016-10-26 13:23 UTC (permalink / raw) To: linux-arm-kernel On 10/26/2016 03:08 PM, Geert Uytterhoeven wrote: >> Here's the set of 8 patches against Simon Horman's 'renesas.git' repo's >> 'renesas-devel-20161021-v4.9-rc1' tag. I'm adding the device tree support for >> the R8A7743-based SK-RZG1M board. The SoC is close to R8A7791 and the board >> seems identical to the R8A7791/Porter board. The device tree patches depend on >> the R8A7743 CPG/MSSR driver series just posted in order to compile and work. > > They depend only on "[PATCH v3 1/2] ARM: shmobile: r8a7743: add CPG clock > index macros" of that series, right? > > "[PATCH v3 2/2] clk: renesas: cpg-mssr: add R8A7743 support" is not needed, How would "clocks" props _work_ without this patch? > and introduces an additional dependency on "[PATCH 1/3] clk: renesas: > cpg-mssr: add common R-Car Gen2 support". Yes, of course... > Gr{oetje,eeting}s, > > Geert MBR, Sergei ^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH v4 0/7] Add R8A7743/SK-RZG1M board support 2016-10-26 13:23 ` Sergei Shtylyov @ 2016-10-26 13:27 ` Geert Uytterhoeven 2016-10-27 7:06 ` Simon Horman 0 siblings, 1 reply; 12+ messages in thread From: Geert Uytterhoeven @ 2016-10-26 13:27 UTC (permalink / raw) To: linux-arm-kernel On Wed, Oct 26, 2016 at 3:23 PM, Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> wrote: > On 10/26/2016 03:08 PM, Geert Uytterhoeven wrote: >>> Here's the set of 8 patches against Simon Horman's 'renesas.git' >>> repo's >>> 'renesas-devel-20161021-v4.9-rc1' tag. I'm adding the device tree support >>> for >>> the R8A7743-based SK-RZG1M board. The SoC is close to R8A7791 and the >>> board >>> seems identical to the R8A7791/Porter board. The device tree patches >>> depend on >>> the R8A7743 CPG/MSSR driver series just posted in order to compile and >>> work. >> >> >> They depend only on "[PATCH v3 1/2] ARM: shmobile: r8a7743: add CPG clock >> index macros" of that series, right? >> >> "[PATCH v3 2/2] clk: renesas: cpg-mssr: add R8A7743 support" is not >> needed, > > How would "clocks" props _work_ without this patch? Sorry, I was focusing too much on "compile"... Got my coke, switching brain to overdrive mode... Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds ^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH v4 0/7] Add R8A7743/SK-RZG1M board support 2016-10-26 13:27 ` Geert Uytterhoeven @ 2016-10-27 7:06 ` Simon Horman 0 siblings, 0 replies; 12+ messages in thread From: Simon Horman @ 2016-10-27 7:06 UTC (permalink / raw) To: linux-arm-kernel On Wed, Oct 26, 2016 at 03:27:14PM +0200, Geert Uytterhoeven wrote: > On Wed, Oct 26, 2016 at 3:23 PM, Sergei Shtylyov > <sergei.shtylyov@cogentembedded.com> wrote: > > On 10/26/2016 03:08 PM, Geert Uytterhoeven wrote: > >>> Here's the set of 8 patches against Simon Horman's 'renesas.git' > >>> repo's > >>> 'renesas-devel-20161021-v4.9-rc1' tag. I'm adding the device tree support > >>> for > >>> the R8A7743-based SK-RZG1M board. The SoC is close to R8A7791 and the > >>> board > >>> seems identical to the R8A7791/Porter board. The device tree patches > >>> depend on > >>> the R8A7743 CPG/MSSR driver series just posted in order to compile and > >>> work. > >> > >> > >> They depend only on "[PATCH v3 1/2] ARM: shmobile: r8a7743: add CPG clock > >> index macros" of that series, right? > >> > >> "[PATCH v3 2/2] clk: renesas: cpg-mssr: add R8A7743 support" is not > >> needed, > > > > How would "clocks" props _work_ without this patch? > > Sorry, I was focusing too much on "compile"... > > Got my coke, switching brain to overdrive mode... As we are talking about adding support for a new SoC I would be happy to queue up code in my tree that compiles under the assumption that in v4.10 the bits to make it run will appear in other branches. ^ permalink raw reply [flat|nested] 12+ messages in thread
end of thread, other threads:[~2016-10-27 7:06 UTC | newest]
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2016-10-21 20:39 [PATCH v4 0/7] Add R8A7743/SK-RZG1M board support Sergei Shtylyov
2016-10-21 20:40 ` [PATCH v4 1/7] ARM: dts: r8a7743: initial SoC device tree Sergei Shtylyov
2016-10-21 20:41 ` [PATCH v4 2/7] ARM: dts: r8a7743: add SYS-DMAC support Sergei Shtylyov
2016-10-21 20:42 ` [PATCH v4 3/7] ARM: dts: r8a7743: add [H]SCIF{|A|B} support Sergei Shtylyov
2016-10-21 20:45 ` [PATCH v4 4/7] ARM: dts: r8a7743: add Ether support Sergei Shtylyov
2016-10-21 20:46 ` [PATCH v4 5/7] ARM: dts: r8a7743: add IRQC support Sergei Shtylyov
2016-10-21 20:47 ` [PATCH v4 6/7] ARM: dts: sk-rzg1m: initial device tree Sergei Shtylyov
2016-10-21 20:48 ` [PATCH v4 7/7] ARM: dts: sk-rzg1m: add Ether support Sergei Shtylyov
2016-10-26 12:08 ` [PATCH v4 0/7] Add R8A7743/SK-RZG1M board support Geert Uytterhoeven
2016-10-26 13:23 ` Sergei Shtylyov
2016-10-26 13:27 ` Geert Uytterhoeven
2016-10-27 7:06 ` Simon Horman
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