From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 99008C433F5 for ; Tue, 8 Mar 2022 19:51:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-ID:Date:From:Cc:To :Subject:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=0bFpG+B5jietWJw0JzF68Wj7Sr6pPSG3CER+Ed7a63k=; b=Q9uEOIAfhvQhXT 0NMqZ5i32Un0HhKhUrVjZqHaIqrfLvNNOEz84HUHG7qnMhFeceg3CdnDDusHzjUce56l+zxa+Q3TY fgR601mxhoAo01OKYjEhKn1U/Czfr3mUKhCaEVTLBOJbLpDu46Gyu1mS67I8XDFskwRX8zVjGg19J gSyz9Gdr9tbZeTs0qdF2qUTYc5unQX3sXM4QHCYc5ku3UvTNWMOtN5vFqS5SJfX8pdhPRV0we/C3A IyXm+m8T9KgSvSjV12ZJnbbW9Lg8RcLGCQ98qByIuol9iL44gZ7ypTBvZrwPsy1997dPaFJRqmA6N J9Egjs7VyJ/BOHkRpkeQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nRfqK-0063le-PM; Tue, 08 Mar 2022 19:50:00 +0000 Received: from ams.source.kernel.org ([145.40.68.75]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nRfqE-0063kB-3M for linux-arm-kernel@lists.infradead.org; Tue, 08 Mar 2022 19:49:55 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 90F31B81BA8; Tue, 8 Mar 2022 19:49:52 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id CBB96C340EF; Tue, 8 Mar 2022 19:49:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linuxfoundation.org; s=korg; t=1646768991; bh=/E//3pxIkIAKZlVOcCT4NmtfWebtL0Ujsn+DJiUI0sc=; h=Subject:To:Cc:From:Date:From; b=1Yp/3wegEdFkBd+rTfcTtFNoO5uMw78xm/ANiMV4gxD5kYYSmjQ+IT+iJU6bbqANl AYzpp3bZg3Qkq3Agy3y6RiWzG/1pajqTfI/9L6vWF2mFWXiT2Fdo8A41+3I1Oewjan vyiD925vEkLe/y7zxYXBezNRidUBlReGNkD+Yzpo= Subject: Patch "arm64: Add Cortex-A510 CPU part definition" has been added to the 5.10-stable tree To: anshuman.khandual@arm.com, catalin.marinas@arm.com, gregkh@linuxfoundation.org, linux-arm-kernel@lists.infradead.org, mathieu.poirier@linaro.org, suzuki.poulose@arm.com, will@kernel.org Cc: From: Date: Tue, 08 Mar 2022 20:49:29 +0100 Message-ID: <1646768969192170@kroah.com> MIME-Version: 1.0 X-stable: commit X-Patchwork-Hint: ignore X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220308_114954_470155_CAA91D72 X-CRM114-Status: GOOD ( 13.93 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This is a note to let you know that I've just added the patch titled arm64: Add Cortex-A510 CPU part definition to the 5.10-stable tree which can be found at: http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary The filename of the patch is: arm64-add-cortex-a510-cpu-part-definition.patch and it can be found in the queue-5.10 subdirectory. If you, or anyone else, feels it should not be added to the stable tree, please let know about it. >From foo@baz Tue Mar 8 08:49:05 PM CET 2022 From: Anshuman Khandual Date: Tue, 25 Jan 2022 19:50:31 +0530 Subject: arm64: Add Cortex-A510 CPU part definition From: Anshuman Khandual commit 53960faf2b731dd2f9ed6e1334634b8ba6286850 upstream. Add the CPU Partnumbers for the new Arm designs. Cc: Catalin Marinas Cc: Will Deacon Cc: Suzuki Poulose Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Reviewed-by: Suzuki K Poulose Acked-by: Catalin Marinas Signed-off-by: Anshuman Khandual Link: https://lore.kernel.org/r/1643120437-14352-2-git-send-email-anshuman.khandual@arm.com Signed-off-by: Mathieu Poirier Signed-off-by: Greg Kroah-Hartman --- arch/arm64/include/asm/cputype.h | 2 ++ 1 file changed, 2 insertions(+) --- a/arch/arm64/include/asm/cputype.h +++ b/arch/arm64/include/asm/cputype.h @@ -73,6 +73,7 @@ #define ARM_CPU_PART_CORTEX_A76 0xD0B #define ARM_CPU_PART_NEOVERSE_N1 0xD0C #define ARM_CPU_PART_CORTEX_A77 0xD0D +#define ARM_CPU_PART_CORTEX_A510 0xD46 #define ARM_CPU_PART_CORTEX_A710 0xD47 #define ARM_CPU_PART_CORTEX_X2 0xD48 #define ARM_CPU_PART_NEOVERSE_N2 0xD49 @@ -116,6 +117,7 @@ #define MIDR_CORTEX_A76 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A76) #define MIDR_NEOVERSE_N1 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N1) #define MIDR_CORTEX_A77 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A77) +#define MIDR_CORTEX_A510 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A510) #define MIDR_CORTEX_A710 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A710) #define MIDR_CORTEX_X2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X2) #define MIDR_NEOVERSE_N2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N2) Patches currently in stable-queue which might be from anshuman.khandual@arm.com are queue-5.10/arm64-add-cortex-a510-cpu-part-definition.patch queue-5.10/arm64-add-neoverse-n2-cortex-a710-cpu-part-definition.patch queue-5.10/arm64-add-cortex-x2-cpu-part-definition.patch _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel