From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B62D6C433EF for ; Sat, 19 Mar 2022 12:54:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-ID:In-Reply-To: Date:From:Cc:To:Subject:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:References: List-Owner; bh=WtEamtWT2GY8gd1yM2T0K1alt3PEhnuzAnVW23tU1Gw=; b=YeNuKdVCRmwbgj 3WBdE1+Z9wB9IT9ibIXfZqkv9JhMFHEb+ZVGJTpHSfliH456BWZ4fvp7f6sSQrc5Pu+vVhlRTgCNW reSKq7/Xdnb+GMZE6R7y7zMl7MD11SfiXWgIbRnmCv6dts1HLeya3HQTodUqhwnx1XzB9hNrBk77q KjjqAhxsRwy9SkGuxaop5IU6EwsH3eXUw+NWV0b3BHvURwDz1qEtuf7h03HHB7usDOZ+1w3j/Am92 kwS85Vr3Qbf+9ABQjigC1zA0/0QR2XpAww/kbFD3QTw+q/pzczbFuKqwcCCgOUb6kYrgmLQie26/i A6gKSK40DJh6qtOjV5NQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nVYZY-003ne4-Dp; Sat, 19 Mar 2022 12:52:44 +0000 Received: from ams.source.kernel.org ([145.40.68.75]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nVYZU-003ndY-U4 for linux-arm-kernel@lists.infradead.org; Sat, 19 Mar 2022 12:52:42 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id B3BD5B80B93; Sat, 19 Mar 2022 12:52:38 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id A71B2C340EC; Sat, 19 Mar 2022 12:52:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linuxfoundation.org; s=korg; t=1647694357; bh=yOxZ2KEBzC2x1OiP2eDluVubx5tlzE4iID6AQLacwY8=; h=Subject:To:Cc:From:Date:In-Reply-To:From; b=KDx522QaxgNsp398c9r17hFg5ljPzBmKDUhqIyUQhYIfouzAUrKfrfbBvAitXJfcB AawdwfA6kmzaXftRuIJ+m4HfPWm5uw9R50KZbkO0Ecg8XRWXxC4MiWxzMIakf+X3hI E+Qnp/CedF1kzlVN5QFra5pbqVnZWYA6NKq7zsI8= Subject: Patch "arm64: Add Cortex-X2 CPU part definition" has been added to the 4.19-stable tree To: anshuman.khandual@arm.com, catalin.marinas@arm.com, gregkh@linuxfoundation.org, james.morse@arm.com, linux-arm-kernel@lists.infradead.org, suzuki.poulose@arm.com, will@kernel.org Cc: From: Date: Sat, 19 Mar 2022 13:52:34 +0100 In-Reply-To: <20220318174842.2321061-4-james.morse@arm.com> Message-ID: <16476943548558@kroah.com> MIME-Version: 1.0 X-stable: commit X-Patchwork-Hint: ignore X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220319_055241_329924_6271BFD9 X-CRM114-Status: GOOD ( 15.01 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This is a note to let you know that I've just added the patch titled arm64: Add Cortex-X2 CPU part definition to the 4.19-stable tree which can be found at: http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary The filename of the patch is: arm64-add-cortex-x2-cpu-part-definition.patch and it can be found in the queue-4.19 subdirectory. If you, or anyone else, feels it should not be added to the stable tree, please let know about it. >From foo@baz Sat Mar 19 01:51:18 PM CET 2022 From: James Morse Date: Fri, 18 Mar 2022 17:48:23 +0000 Subject: arm64: Add Cortex-X2 CPU part definition To: stable@vger.kernel.org Cc: linux-kernel@vger.kernel.org, james.morse@arm.com, catalin.marinas@arm.com Message-ID: <20220318174842.2321061-4-james.morse@arm.com> From: Anshuman Khandual commit 72bb9dcb6c33cfac80282713c2b4f2b254cd24d1 upstream. Add the CPU Partnumbers for the new Arm designs. Cc: Will Deacon Cc: Suzuki Poulose Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual Reviewed-by: Suzuki K Poulose Link: https://lore.kernel.org/r/1642994138-25887-2-git-send-email-anshuman.khandual@arm.com Signed-off-by: Catalin Marinas Signed-off-by: James Morse Signed-off-by: Greg Kroah-Hartman --- arch/arm64/include/asm/cputype.h | 2 ++ 1 file changed, 2 insertions(+) --- a/arch/arm64/include/asm/cputype.h +++ b/arch/arm64/include/asm/cputype.h @@ -83,6 +83,7 @@ #define ARM_CPU_PART_NEOVERSE_N1 0xD0C #define ARM_CPU_PART_CORTEX_A77 0xD0D #define ARM_CPU_PART_CORTEX_A710 0xD47 +#define ARM_CPU_PART_CORTEX_X2 0xD48 #define ARM_CPU_PART_NEOVERSE_N2 0xD49 #define APM_CPU_PART_POTENZA 0x000 @@ -114,6 +115,7 @@ #define MIDR_NEOVERSE_N1 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N1) #define MIDR_CORTEX_A77 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A77) #define MIDR_CORTEX_A710 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A710) +#define MIDR_CORTEX_X2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X2) #define MIDR_NEOVERSE_N2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N2) #define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX) #define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX) Patches currently in stable-queue which might be from james.morse@arm.com are queue-4.19/arm64-entry-add-macro-for-reading-symbol-addresses-from-the-trampoline.patch queue-4.19/arm64-use-the-clearbhb-instruction-in-mitigations.patch queue-4.19/arm64-add-percpu-vectors-for-el1.patch queue-4.19/arm64-entry-free-up-another-register-on-kpti-s-tramp_exit-path.patch queue-4.19/arm64-entry-don-t-assume-tramp_vectors-is-the-start-of-the-vectors.patch queue-4.19/arm64-entry-make-the-trampoline-cleanup-optional.patch queue-4.19/kvm-arm64-add-templates-for-bhb-mitigation-sequences.patch queue-4.19/arm64-entry-add-non-kpti-__bp_harden_el1_vectors-for-mitigations.patch queue-4.19/arm64-add-id_aa64isar2_el1-sys-register.patch queue-4.19/kvm-arm64-allow-smccc_arch_workaround_3-to-be-discovered-and-migrated.patch queue-4.19/arm64-add-neoverse-n2-cortex-a710-cpu-part-definition.patch queue-4.19/arm64-entry-move-trampoline-macros-out-of-ifdef-d-section.patch queue-4.19/arm64-entry-allow-tramp_alias-to-access-symbols-after-the-4k-boundary.patch queue-4.19/arm64-add-part-number-for-arm-cortex-a77.patch queue-4.19/arm64-entry-move-the-trampoline-data-page-before-the-text-page.patch queue-4.19/arm64-entry.s-add-ventry-overflow-sanity-checks.patch queue-4.19/arm64-entry-add-vectors-that-have-the-bhb-mitigation-sequences.patch queue-4.19/arm64-mitigate-spectre-style-branch-history-side-channels.patch queue-4.19/arm64-entry-allow-the-trampoline-text-to-occupy-multiple-pages.patch queue-4.19/arm64-proton-pack-report-spectre-bhb-vulnerabilities-as-part-of-spectre-v2.patch queue-4.19/arm64-add-cortex-x2-cpu-part-definition.patch queue-4.19/arm64-entry-make-the-kpti-trampoline-s-kpti-sequence-optional.patch _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel