From mboxrd@z Thu Jan  1 00:00:00 1970
From: heiko@sntech.de (Heiko =?ISO-8859-1?Q?St=FCbner?=)
Date: Wed, 26 Mar 2014 00:56:15 +0100
Subject: [PATCH 0/2] pinctrl: rockchip: fix handling of first pinbank
In-Reply-To: <20140325194357.GA27520@gmail.com>
References: <1395700561-3793-1-git-send-email-b.galvani@gmail.com>
 <2790002.5U2DHYmUbK@diego> <20140325194357.GA27520@gmail.com>
Message-ID: <1647754.qr1tAySXax@diego>
To: linux-arm-kernel@lists.infradead.org
List-Id: linux-arm-kernel.lists.infradead.org

Am Dienstag, 25. M?rz 2014, 20:43:59 schrieb Beniamino Galvani:
> On Tue, Mar 25, 2014 at 12:14:42AM +0100, Heiko St?bner wrote:
> > GPIO0 only has the second two IOMUX registers:
> > - GRF_GPIO0C_IOMUX at 0x68
> > - GRF_GPIO0D_IOMUX at 0x6c
> > which I guess is where my mistake comes from.

[...] 

> On radxa rock schematic pins GPIO0A* and GPIO0B* are labeled only as
> gpios, without alternate functions like other pins; my guess is that
> on rk3188 they can only act as gpios and so mux registers are not
> needed for them.

That was my guess too - especially as the registers are also missing.

Therefore I put together the following two patches to go on top of
your patch and also make rockchip_set_mux honor this situation.


Heiko Stuebner (2):
  pinctrl: rockchip: add return value to rockchip_set_mux
  pinctrl: rockchip: handle first half of rk3188-bank0 correctly

 drivers/pinctrl/pinctrl-rockchip.c | 46 ++++++++++++++++++++++++++++++++------
 1 file changed, 39 insertions(+), 7 deletions(-)

-- 
1.9.0