From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BA49BC433F5 for ; Mon, 23 May 2022 12:26:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:List-Subscribe:List-Help: List-Post:List-Archive:List-Unsubscribe:List-Id:Message-Id:Date:Subject:Cc:To :From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=otSzTHuz8+1+9Nl55R7d6OM1bfmwPXPYZr6shYTpmXE=; b=un7svhCTWboNk7 H+H+bcBFPRnoM3coffGdRfYV84c70I3+g90Gaiz9t/DcHnPzUBHEkcr/aWhLQL4xw1Y1eUYQctnwJ wKiIpULwN/BL7mZ/nPxYEEEFM3UCFqxrGCA5Uo2lkOCImMvpnUl9f0T9GZmd43g+snpFu2haRqTBN f8SOTOVMQ2YH61ySGCbp6od0fq/RGg1I1kLDTGhhg53DvWIGT5A2NtxsKNZywE69Y9F/DI+z/penH CZTYR+xGH13S7LF5MuGMadn736OMXXG2GxrPkoTw9MqL4rDq1wKtM34ON87wfgAU2pNL0TcfX1NLu /BznWQfw7KVR6U2QBE7A==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nt77K-0046mF-I2; Mon, 23 May 2022 12:24:59 +0000 Received: from alexa-out.qualcomm.com ([129.46.98.28]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nt6ZW-003qzL-AK for linux-arm-kernel@lists.infradead.org; Mon, 23 May 2022 11:50:08 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1653306602; x=1684842602; h=from:to:cc:subject:date:message-id; bh=WmKCF3EyU++9G579lZKMTRj5Z0y/zWQdzCZSNlAEd+Q=; b=puIsDm7wMwPxjxuo5HvJRCHufkieuiBiFLD/jgKFZ/Pw5SSCFHVtstuq FeQwodANqMWQpgsMsypEnQ5GA9JyzeeQFE0WHy+I1UA8QKVUFnpqOSh9Z HBN78W+93M82eOw4Fl74NuPJ+ZKoLRx7I92zvHv6Hdsg7Z7Dtsn77J4m9 w=; Received: from ironmsg08-lv.qualcomm.com ([10.47.202.152]) by alexa-out.qualcomm.com with ESMTP; 23 May 2022 04:49:58 -0700 X-QCInternal: smtphost Received: from ironmsg01-blr.qualcomm.com ([10.86.208.130]) by ironmsg08-lv.qualcomm.com with ESMTP/TLS/AES256-SHA; 23 May 2022 04:49:57 -0700 X-QCInternal: smtphost Received: from hu-c-spathi-hyd.qualcomm.com (HELO hu-sgudaval-hyd.qualcomm.com) ([10.213.108.59]) by ironmsg01-blr.qualcomm.com with ESMTP; 23 May 2022 17:19:41 +0530 Received: by hu-sgudaval-hyd.qualcomm.com (Postfix, from userid 212714) id 4EDBA39C8; Mon, 23 May 2022 17:19:40 +0530 (+0530) From: Srinivasarao Pathipati To: will@kernel.org, mark.rutland@arm.com, peterz@infradead.org, mingo@redhat.com, acme@kernel.org, alexander.shishkin@linux.intel.com, jolsa@kernel.org, namhyung@kernel.org, catalin.marinas@arm.com, linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Srinivasarao Pathipati Subject: [PATCH V5] arm64: perf: Make exporting of pmu events configurable Date: Mon, 23 May 2022 17:19:34 +0530 Message-Id: <1653306574-20946-1-git-send-email-quic_c_spathi@quicinc.com> X-Mailer: git-send-email 2.7.4 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220523_045002_471942_3C91B03F X-CRM114-Status: GOOD ( 16.85 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The PMU export bit (PMCR_EL0.X) is getting reset during pmu reset, Make is configurable using sysctls to enable/disable at runtime. It can also be enabled at early bootup with kernel arguments. Signed-off-by: Srinivasarao Pathipati --- Changes since V4: - Registering sysctls dynamically for only arm64 as suggested by Will - Not removed the code to configure with kernel parameters as the sysctl's kernel parameter(sysctl.kernel.export_pmu_events) is not working at early bootup. pmu_reset() getting called before sysctl's kernel parameter is set. Changes since V3: - export bit is now configurable with sysctl - enabling export bit on reset instead of retaining Changes since V2: Done below changes as per Will's comments - enabling pmcr_x now configurable with kernel parameters and by default it is disabled. Changes since V1: - Preserving only PMCR_X bit as per Robin Murphy's comment. --- Documentation/admin-guide/kernel-parameters.txt | 5 +++++ Documentation/admin-guide/sysctl/kernel.rst | 9 +++++++++ arch/arm64/kernel/perf_event.c | 24 ++++++++++++++++++++++++ 3 files changed, 38 insertions(+) diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt index de3da15..2bf1187 100644 --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -5150,6 +5150,11 @@ Useful for devices that are detected asynchronously (e.g. USB and MMC devices). + export_pmu_events + [KNL,ARM64] Sets the PMU export bit (PMCR_EL0.X), which enables + the exporting of events over an IMPLEMENTATION DEFINED PMU event + export bus to another device. + retain_initrd [RAM] Keep initrd memory after extraction rfkill.default_state= diff --git a/Documentation/admin-guide/sysctl/kernel.rst b/Documentation/admin-guide/sysctl/kernel.rst index ddccd10..db42d4c 100644 --- a/Documentation/admin-guide/sysctl/kernel.rst +++ b/Documentation/admin-guide/sysctl/kernel.rst @@ -892,6 +892,15 @@ The default value is 0 (access disabled). See Documentation/arm64/perf.rst for more information. +export_pmu_events (arm64 only) +============================== +Controls the PMU export bit (PMCR_EL0.X), which enables the exporting of +events over an IMPLEMENTATION DEFINED PMU event export bus to another device. + +0: disables exporting of events (default). + +1: enables exporting of events. + pid_max ======= diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c index cb69ff1..d93e7c4 100644 --- a/arch/arm64/kernel/perf_event.c +++ b/arch/arm64/kernel/perf_event.c @@ -298,6 +298,7 @@ PMU_FORMAT_ATTR(long, "config1:0"); PMU_FORMAT_ATTR(rdpmc, "config1:1"); static int sysctl_perf_user_access __read_mostly; +static int sysctl_export_pmu_events __read_mostly; static inline bool armv8pmu_event_is_64bit(struct perf_event *event) { @@ -1025,6 +1026,17 @@ static int armv8pmu_filter_match(struct perf_event *event) return evtype != ARMV8_PMUV3_PERFCTR_CHAIN; } +static int __init export_pmu_events(char *str) +{ + /* Enable exporting of pmu events at early bootup with kernel + * arguments. + */ + sysctl_export_pmu_events = 1; + return 0; +} + +early_param("export_pmu_events", export_pmu_events); + static void armv8pmu_reset(void *info) { struct arm_pmu *cpu_pmu = (struct arm_pmu *)info; @@ -1047,6 +1059,9 @@ static void armv8pmu_reset(void *info) if (armv8pmu_has_long_event(cpu_pmu)) pmcr |= ARMV8_PMU_PMCR_LP; + if (sysctl_export_pmu_events) + pmcr |= ARMV8_PMU_PMCR_X; + armv8pmu_pmcr_write(pmcr); } @@ -1221,6 +1236,15 @@ static struct ctl_table armv8_pmu_sysctl_table[] = { .extra1 = SYSCTL_ZERO, .extra2 = SYSCTL_ONE, }, + { + .procname = "export_pmu_events", + .data = &sysctl_export_pmu_events, + .maxlen = sizeof(unsigned int), + .mode = 0644, + .proc_handler = proc_dointvec_minmax, + .extra1 = SYSCTL_ZERO, + .extra2 = SYSCTL_ONE, + }, { } }; -- 2.7.4 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel