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Sat, 3 Oct 2026 06:12:20 -0400 (EDT) X-Mailer: MessagingEngine.com Webmail Interface MIME-Version: 1.0 X-ThreadId: A3bqS_zWz5jN Date: Sat, 03 Oct 2026 12:12:00 +0200 From: "Arnd Bergmann" To: "Karl Mehltretter" , "Russell King" , "Miguel Ojeda" Cc: "Boqun Feng" , "Gary Guo" , =?UTF-8?Q?Bj=C3=B6rn_Roy_Baron?= , "Benno Lossin" , "Andreas Hindborg" , "Alice Ryhl" , "Trevor Gross" , "Danilo Krummrich" , "Daniel Almeida" , "Tamir Duberstein" , "Alexandre Courbot" , =?UTF-8?Q?Onur_=C3=96zkan?= , "Linus Walleij" , "Christian Schrefl" , "Bradley Morgan" , "Paul E. McKenney" , "Nathan Chancellor" , "Nick Desaulniers" , "Bill Wendling" , "Justin Stitt" , linux-arm-kernel@lists.infradead.org, rust-for-linux@vger.kernel.org, llvm@lists.linux.dev, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, "Krzysztof Kozlowski" Message-Id: <1682542c-b5c7-4031-9d8b-7ba1d0a3ee19@app.fastmail.com> In-Reply-To: <20261003093827.77857-2-kmehltretter@gmail.com> References: <20261003093827.77857-1-kmehltretter@gmail.com> <20261003093827.77857-2-kmehltretter@gmail.com> Subject: Re: [PATCH 1/2] ARM: cmpxchg: support 2-byte xchg() on pre-ARMv6 CPUs Content-Type: text/plain Content-Transfer-Encoding: 7bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20261003_031240_805335_891D8A65 X-CRM114-Status: GOOD ( 12.04 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Sat, Oct 3, 2026, at 11:38, Karl Mehltretter wrote: > Pre-ARMv6 CPUs have no halfword swp, so __arch_xchg() only handles 1- > and 4-byte exchanges there and turns any other size into a link error > via __bad_xchg(). Note that 16-bit atomics are only in ARMv6K (1136r1, 1176), not ARMv6 (1136r0). > No C code needs a 16-bit xchg() on these CPUs, but the Rust atomic > helpers in rust/helpers/atomic_ext.c provide xchg() for Atomic > unconditionally, so building with CONFIG_RUST=y for ARMv5 fails: > > ld.lld: error: undefined symbol: __bad_xchg > >>> referenced by helpers.c > >>> rust/helpers/helpers.o:(rust_helper_atomic_i16_xchg) > > Implement the 2-byte case with interrupts disabled, as the pre-ARMv6 > atomic_t operations already do. This is safe because SMP requires > ARMv6K or later. This was previously impossible because you could have ARMv6 kernels with SMP enabled, but now that Krzysztof has merged my series to remove OMAP2 and i.MX6, this should work. If anyone wants to backport this to older kernels, they would also require d70242427110 ("ARM: rework ARM11 CPU selection logic"). Otherwise, this looks good, Acked-by: Arnd Bergmann Arnd