From: wangyushan <wangyushan12@huawei.com>
To: Krzysztof Kozlowski <krzk@kernel.org>
Cc: Arnd Bergmann <arnd@arndb.de>,
Alexandre Belloni <alexandre.belloni@bootlin.com>,
Drew Fustini <fustini@kernel.org>,
"Jonathan Cameron" <Jonathan.Cameron@huawei.com>,
Linus Walleij <linus.walleij@linaro.org>,
Will Deacon <will@kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-kernel@vger.kernel.org>, <fanghao11@huawei.com>,
<linuxarm@huawei.com>, <liuyonglong@huawei.com>,
<prime.zeng@hisilicon.com>, Zhou Wang <wangzhou1@hisilicon.com>,
Wei Xu <xuwei5@hisilicon.com>
Subject: Re: [PATCH 1/3] soc cache: L3 cache driver for HiSilicon SoC
Date: Thu, 5 Feb 2026 19:30:59 +0800 [thread overview]
Message-ID: <16b06f6f-e251-4fb6-9c82-e9a366351a02@huawei.com> (raw)
In-Reply-To: <82c73122-4d0e-45f5-b1b4-3cf743353fd6@kernel.org>
On 2/5/2026 7:23 PM, Krzysztof Kozlowski wrote:
> On 05/02/2026 12:19, wangyushan wrote:
>>
>> On 2/5/2026 5:37 PM, Krzysztof Kozlowski wrote:
>>> On 03/02/2026 18:19, Arnd Bergmann wrote:
>>>> On Tue, Feb 3, 2026, at 17:18, Yushan Wang wrote:
>>>>> The driver will create a file of `/dev/hisi_l3c` on init, mmap
>>>>> operations to it will allocate a memory region that is guaranteed to be
>>>>> placed in L3 cache.
>>>>>
>>>>> The driver also provides unmap() to deallocated the locked memory.
>>>>>
>>>>> The driver also provides an ioctl interface for user to get cache lock
>>>>> information, such as lock restrictions and locked sizes.
>>>>>
>>>>> Signed-off-by: Yushan Wang <wangyushan12@huawei.com>
>>>>
>>>> Hi Yushan,
>>>>
>>>> Thanks for your submission. Since we are in the last week of
>>>> the merge window, this is not going to be linux-7.0 material,
>>>> but I'll have a quick look for now.
>>>
>>>
>>> To be clear - this is a v3 but with removed previous history...
>>>
>>> Previous version:
>>> https://lore.kernel.org/all/20251217102357.1730573-2-wangyushan12@huawei.com/
>>>
>>> Or even v4?
>>>
>>> https://lore.kernel.org/all/20250122065803.3363926-2-wangyushan12@huawei.com/
>>>
>>> Yushan, please start versioning your patches correctly. Use b4 or git
>>> format-patch -vx
>>
>> Hi Krzysztof,
>>
>> Sorry about the confusing versions, the complete history is as below:
>>
>> Link to v1: https://lore.kernel.org/all/20250107132907.3521574-1-wangyushan12@huawei.com
>>
>> Link to v2: https://lore.kernel.org/all/20250122065803.3363926-1-wangyushan12@huawei.com/
>>
>> Link to RFC v1: https://lore.kernel.org/all/20251125080542.3721829-1-wangyushan12@huawei.com/
>>
>> Link to RFC v2: https://lore.kernel.org/all/20251217102357.1730573-1-wangyushan12@huawei.com/
>>
>> Link to v1 again (this message): https://lore.kernel.org/all/20260203161843.649417-1-wangyushan12@huawei.com/
>>
>>>
>>> Otherwise, please explain us how can we compare it with `b4 diff` with
>>> previous version?
>>>
>>> Sending something AGAIN as v1 ignoring entire previous submission is
>>> clear no go. Like you are trying till it succeeds. Negative review?
>>> Let's try from v1 this time...
>>>
>>> This is not correct and it should not be my task to find your previous
>>> discussions and decipher this v1.
>>
>> I did spin 2 versions to mainline as the actual v1, the thread was quiet.
>> Then I made a major refactor to it and sent it as RFC, the thread went
>> quiet again but some compile check issues popped up. I spinned 2
>> versions of RFC for the compile issues and removed RFC in this version
>> since no strong objection showed up.
>>
>> Apologize that I broke the rules and any inconvenience caused by it.
>> As there's little discussion in previous patches, is it OK that we start
>> here as v1?
>
> No, it is not okay. Your patchset continues and entire previous feedback
> and history is important. Otherwise why would I review this if I can as
> well ignore it and wait for next year you sending another v1?
Sorry, I will correct the version numbers in next versions, with whole
history and explanations about the mess.
Sincerely apologies, I won't hide the versions again.
Yushan
next prev parent reply other threads:[~2026-02-05 11:31 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-02-03 16:18 [PATCH 0/3] soc: Enable cache lockdown for HiSilicon L3 cache Yushan Wang
2026-02-03 16:18 ` [PATCH 1/3] soc cache: L3 cache driver for HiSilicon SoC Yushan Wang
2026-02-03 17:19 ` Arnd Bergmann
2026-02-04 9:51 ` wangyushan
2026-02-05 9:37 ` Krzysztof Kozlowski
2026-02-05 11:19 ` wangyushan
2026-02-05 11:23 ` Krzysztof Kozlowski
2026-02-05 11:30 ` wangyushan [this message]
2026-02-04 0:10 ` Linus Walleij
2026-02-04 9:53 ` wangyushan
2026-02-04 10:06 ` Linus Walleij
2026-02-04 13:40 ` Jonathan Cameron
2026-02-04 13:44 ` Jonathan Cameron
2026-02-05 2:20 ` SeongJae Park
2026-02-05 9:12 ` Linus Walleij
2026-02-05 10:18 ` Jonathan Cameron
2026-02-05 13:47 ` Linus Walleij
2026-02-05 14:38 ` Arnd Bergmann
2026-02-06 8:05 ` Linus Walleij
2026-02-05 14:37 ` Ben Horgan
2026-02-06 9:54 ` wangyushan
2026-02-06 16:15 ` Ben Horgan
2026-02-06 10:07 ` wangyushan
2026-02-06 10:44 ` Arnd Bergmann
2026-02-06 12:44 ` Linus Walleij
2026-02-04 2:47 ` kernel test robot
2026-02-03 16:18 ` [PATCH 2/3] soc cache: L3 cache lockdown support " Yushan Wang
2026-02-03 16:18 ` [PATCH 3/3] Documentation: soc cache: Add documentation to HiSilicon SoC cache Yushan Wang
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