* [PATCH v6 1/3] dt-bindings: arm: fsl: add i.MX95 19x19 EVK board
2024-06-05 1:22 [PATCH v6 0/3] arm64: dts: add i.MX95 and EVK board Peng Fan (OSS)
@ 2024-06-05 1:22 ` Peng Fan (OSS)
2024-06-05 1:22 ` [PATCH v6 3/3] arm64: dts: freescale: add i.MX95 19x19 EVK minimal board dts Peng Fan (OSS)
2024-06-05 13:11 ` [PATCH v6 0/3] arm64: dts: add i.MX95 and EVK board Rob Herring (Arm)
2 siblings, 0 replies; 7+ messages in thread
From: Peng Fan (OSS) @ 2024-06-05 1:22 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam
Cc: devicetree, linux-kernel, imx, linux-arm-kernel, Alexander Stein,
Peng Fan, Conor Dooley
From: Peng Fan <peng.fan@nxp.com>
Add DT compatible string for NXP i.MX95 19x19 EVK board.
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
Documentation/devicetree/bindings/arm/fsl.yaml | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml
index 6d185d09cb6a..5c9014087c17 100644
--- a/Documentation/devicetree/bindings/arm/fsl.yaml
+++ b/Documentation/devicetree/bindings/arm/fsl.yaml
@@ -1275,6 +1275,12 @@ properties:
- fsl,imx93-11x11-evk # i.MX93 11x11 EVK Board
- const: fsl,imx93
+ - description: i.MX95 based Boards
+ items:
+ - enum:
+ - fsl,imx95-19x19-evk # i.MX95 19x19 EVK Board
+ - const: fsl,imx95
+
- description: i.MXRT1050 based Boards
items:
- enum:
--
2.37.1
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^ permalink raw reply related [flat|nested] 7+ messages in thread* [PATCH v6 3/3] arm64: dts: freescale: add i.MX95 19x19 EVK minimal board dts
2024-06-05 1:22 [PATCH v6 0/3] arm64: dts: add i.MX95 and EVK board Peng Fan (OSS)
2024-06-05 1:22 ` [PATCH v6 1/3] dt-bindings: arm: fsl: add i.MX95 19x19 " Peng Fan (OSS)
@ 2024-06-05 1:22 ` Peng Fan (OSS)
2024-06-05 3:34 ` Amit Singh Tomar
2024-06-17 1:09 ` Shawn Guo
2024-06-05 13:11 ` [PATCH v6 0/3] arm64: dts: add i.MX95 and EVK board Rob Herring (Arm)
2 siblings, 2 replies; 7+ messages in thread
From: Peng Fan (OSS) @ 2024-06-05 1:22 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam
Cc: devicetree, linux-kernel, imx, linux-arm-kernel, Alexander Stein,
Peng Fan
From: Peng Fan <peng.fan@nxp.com>
Add a minimal dts for i.MX95 19x19 EVK board:
- lpuart1 as console
- sdhc1/2 as storage
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
arch/arm64/boot/dts/freescale/Makefile | 1 +
arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts | 200 ++++++++++++++++++++++
2 files changed, 201 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
index 1b1e4db02071..c3fef4e4d8dd 100644
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -239,6 +239,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx93-phyboard-segin.dtb
dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba93xxca.dtb
dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba93xxla.dtb
dtb-$(CONFIG_ARCH_MXC) += imx93-var-som-symphony.dtb
+dtb-$(CONFIG_ARCH_MXC) += imx95-19x19-evk.dtb
imx8mm-venice-gw72xx-0x-imx219-dtbs := imx8mm-venice-gw72xx-0x.dtb imx8mm-venice-gw72xx-0x-imx219.dtbo
imx8mm-venice-gw72xx-0x-rpidsi-dtbs := imx8mm-venice-gw72xx-0x.dtb imx8mm-venice-gw72xx-0x-rpidsi.dtbo
diff --git a/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts b/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts
new file mode 100644
index 000000000000..2c2f3cfbe11a
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts
@@ -0,0 +1,200 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2024 NXP
+ */
+
+/dts-v1/;
+
+#include "imx95.dtsi"
+
+/ {
+ model = "NXP i.MX95 19X19 board";
+ compatible = "fsl,imx95-19x19-evk", "fsl,imx95";
+
+ aliases {
+ mmc0 = &usdhc1;
+ mmc1 = &usdhc2;
+ serial0 = &lpuart1;
+ };
+
+ chosen {
+ stdout-path = &lpuart1;
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x0 0x80000000 0 0x80000000>;
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ linux_cma: linux,cma {
+ compatible = "shared-dma-pool";
+ alloc-ranges = <0 0x80000000 0 0x7F000000>;
+ size = <0 0x3c000000>;
+ linux,cma-default;
+ reusable;
+ };
+ };
+
+ reg_usdhc2_vmmc: regulator-usdhc2 {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
+ regulator-name = "VDD_SD2_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>;
+ off-on-delay-us = <12000>;
+ enable-active-high;
+ };
+};
+
+&lpuart1 {
+ /* console */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ status = "okay";
+};
+
+&mu7 {
+ status = "okay";
+};
+
+&usdhc1 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
+ pinctrl-0 = <&pinctrl_usdhc1>;
+ pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
+ pinctrl-3 = <&pinctrl_usdhc1>;
+ bus-width = <8>;
+ non-removable;
+ no-sdio;
+ no-sd;
+ status = "okay";
+};
+
+&usdhc2 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
+ pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-3 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+ cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
+ vmmc-supply = <®_usdhc2_vmmc>;
+ bus-width = <4>;
+ status = "okay";
+};
+
+&wdog3 {
+ fsl,ext-reset-output;
+ status = "okay";
+};
+
+&scmi_iomuxc {
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ IMX95_PAD_UART1_RXD__AONMIX_TOP_LPUART1_RX 0x31e
+ IMX95_PAD_UART1_TXD__AONMIX_TOP_LPUART1_TX 0x31e
+ >;
+ };
+
+ pinctrl_usdhc1: usdhc1grp {
+ fsl,pins = <
+ IMX95_PAD_SD1_CLK__USDHC1_CLK 0x158e
+ IMX95_PAD_SD1_CMD__USDHC1_CMD 0x138e
+ IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x138e
+ IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x138e
+ IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x138e
+ IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x138e
+ IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x138e
+ IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x138e
+ IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x138e
+ IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x138e
+ IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x158e
+ >;
+ };
+
+ pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
+ fsl,pins = <
+ IMX95_PAD_SD1_CLK__USDHC1_CLK 0x158e
+ IMX95_PAD_SD1_CMD__USDHC1_CMD 0x138e
+ IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x138e
+ IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x138e
+ IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x138e
+ IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x138e
+ IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x138e
+ IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x138e
+ IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x138e
+ IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x138e
+ IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x158e
+ >;
+ };
+
+ pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
+ fsl,pins = <
+ IMX95_PAD_SD1_CLK__USDHC1_CLK 0x15fe
+ IMX95_PAD_SD1_CMD__USDHC1_CMD 0x13fe
+ IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe
+ IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe
+ IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe
+ IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe
+ IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe
+ IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe
+ IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe
+ IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe
+ IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe
+ >;
+ };
+
+ pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
+ fsl,pins = <
+ IMX95_PAD_SD2_RESET_B__GPIO3_IO_BIT7 0x31e
+ >;
+ };
+
+ pinctrl_usdhc2_gpio: usdhc2gpiogrp {
+ fsl,pins = <
+ IMX95_PAD_SD2_CD_B__GPIO3_IO_BIT0 0x31e
+ >;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ IMX95_PAD_SD2_CLK__USDHC2_CLK 0x158e
+ IMX95_PAD_SD2_CMD__USDHC2_CMD 0x138e
+ IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x138e
+ IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x138e
+ IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x138e
+ IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x138e
+ IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
+ >;
+ };
+
+ pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
+ fsl,pins = <
+ IMX95_PAD_SD2_CLK__USDHC2_CLK 0x158e
+ IMX95_PAD_SD2_CMD__USDHC2_CMD 0x138e
+ IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x138e
+ IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x138e
+ IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x138e
+ IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x138e
+ IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
+ >;
+ };
+
+ pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
+ fsl,pins = <
+ IMX95_PAD_SD2_CLK__USDHC2_CLK 0x15fe
+ IMX95_PAD_SD2_CMD__USDHC2_CMD 0x13fe
+ IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x13fe
+ IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x13fe
+ IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x13fe
+ IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x13fe
+ IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
+ >;
+ };
+};
--
2.37.1
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^ permalink raw reply related [flat|nested] 7+ messages in thread* [PATCH v6 3/3] arm64: dts: freescale: add i.MX95 19x19 EVK minimal board dts
2024-06-05 1:22 ` [PATCH v6 3/3] arm64: dts: freescale: add i.MX95 19x19 EVK minimal board dts Peng Fan (OSS)
@ 2024-06-05 3:34 ` Amit Singh Tomar
2024-06-17 1:09 ` Shawn Guo
1 sibling, 0 replies; 7+ messages in thread
From: Amit Singh Tomar @ 2024-06-05 3:34 UTC (permalink / raw)
To: Peng Fan (OSS), Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Shawn Guo, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam
Cc: devicetree, linux-kernel, imx, linux-arm-kernel, Alexander Stein,
Peng Fan
> From: Peng Fan <peng.fan@nxp.com>
>
> Add a minimal dts for i.MX95 19x19 EVK board:
> - lpuart1 as console
> - sdhc1/2 as storage
>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> ---
> arch/arm64/boot/dts/freescale/Makefile | 1 +
> arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts | 200 ++++++++++++++++++++++
> 2 files changed, 201 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
> index 1b1e4db02071..c3fef4e4d8dd 100644
> --- a/arch/arm64/boot/dts/freescale/Makefile
> +++ b/arch/arm64/boot/dts/freescale/Makefile
> @@ -239,6 +239,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx93-phyboard-segin.dtb
> dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba93xxca.dtb
> dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba93xxla.dtb
> dtb-$(CONFIG_ARCH_MXC) += imx93-var-som-symphony.dtb
> +dtb-$(CONFIG_ARCH_MXC) += imx95-19x19-evk.dtb
>
> imx8mm-venice-gw72xx-0x-imx219-dtbs := imx8mm-venice-gw72xx-0x.dtb imx8mm-venice-gw72xx-0x-imx219.dtbo
> imx8mm-venice-gw72xx-0x-rpidsi-dtbs := imx8mm-venice-gw72xx-0x.dtb imx8mm-venice-gw72xx-0x-rpidsi.dtbo
> diff --git a/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts b/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts
> new file mode 100644
> index 000000000000..2c2f3cfbe11a
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts
> @@ -0,0 +1,200 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright 2024 NXP
> + */
> +
> +/dts-v1/;
> +
> +#include "imx95.dtsi"
> +
> +/ {
> + model = "NXP i.MX95 19X19 board";
> + compatible = "fsl,imx95-19x19-evk", "fsl,imx95";
> +
> + aliases {
> + mmc0 = &usdhc1;
> + mmc1 = &usdhc2;
> + serial0 = &lpuart1;
> + };
> +
> + chosen {
> + stdout-path = &lpuart1;
> + };
> +
> + memory@80000000 {
> + device_type = "memory";
> + reg = <0x0 0x80000000 0 0x80000000>;
> + };
> +
> + reserved-memory {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + linux_cma: linux,cma {
> + compatible = "shared-dma-pool";
> + alloc-ranges = <0 0x80000000 0 0x7F000000>;
nitpick: Please use the lower case (0x7f...) for length parameter.
> + size = <0 0x3c000000>;
> + linux,cma-default;
> + reusable;
> + };
> + };
> +
> + reg_usdhc2_vmmc: regulator-usdhc2 {
> + compatible = "regulator-fixed";
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
> + regulator-name = "VDD_SD2_3V3";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>;
> + off-on-delay-us = <12000>;
> + enable-active-high;
> + };
> +};
> +
> +&lpuart1 {
> + /* console */
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_uart1>;
> + status = "okay";
> +};
> +
> +&mu7 {
> + status = "okay";
> +};
> +
> +&usdhc1 {
> + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
> + pinctrl-0 = <&pinctrl_usdhc1>;
> + pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
> + pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
> + pinctrl-3 = <&pinctrl_usdhc1>;
> + bus-width = <8>;
> + non-removable;
> + no-sdio;
> + no-sd;
> + status = "okay";
> +};
> +
> +&usdhc2 {
> + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
> + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
> + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
> + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
> + pinctrl-3 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
> + cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
> + vmmc-supply = <®_usdhc2_vmmc>;
> + bus-width = <4>;
> + status = "okay";
> +};
> +
> +&wdog3 {
> + fsl,ext-reset-output;
> + status = "okay";
> +};
> +
> +&scmi_iomuxc {
> + pinctrl_uart1: uart1grp {
> + fsl,pins = <
> + IMX95_PAD_UART1_RXD__AONMIX_TOP_LPUART1_RX 0x31e
> + IMX95_PAD_UART1_TXD__AONMIX_TOP_LPUART1_TX 0x31e
> + >;
> + };
> +
> + pinctrl_usdhc1: usdhc1grp {
> + fsl,pins = <
> + IMX95_PAD_SD1_CLK__USDHC1_CLK 0x158e
> + IMX95_PAD_SD1_CMD__USDHC1_CMD 0x138e
> + IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x138e
> + IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x138e
> + IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x138e
> + IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x138e
> + IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x138e
> + IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x138e
> + IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x138e
> + IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x138e
> + IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x158e
> + >;
> + };
> +
> + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
> + fsl,pins = <
> + IMX95_PAD_SD1_CLK__USDHC1_CLK 0x158e
> + IMX95_PAD_SD1_CMD__USDHC1_CMD 0x138e
> + IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x138e
> + IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x138e
> + IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x138e
> + IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x138e
> + IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x138e
> + IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x138e
> + IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x138e
> + IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x138e
> + IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x158e
> + >;
> + };
> +
> + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
> + fsl,pins = <
> + IMX95_PAD_SD1_CLK__USDHC1_CLK 0x15fe
> + IMX95_PAD_SD1_CMD__USDHC1_CMD 0x13fe
> + IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe
> + IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe
> + IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe
> + IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe
> + IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe
> + IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe
> + IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe
> + IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe
> + IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe
> + >;
> + };
> +
> + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
> + fsl,pins = <
> + IMX95_PAD_SD2_RESET_B__GPIO3_IO_BIT7 0x31e
> + >;
> + };
> +
> + pinctrl_usdhc2_gpio: usdhc2gpiogrp {
> + fsl,pins = <
> + IMX95_PAD_SD2_CD_B__GPIO3_IO_BIT0 0x31e
> + >;
> + };
> +
> + pinctrl_usdhc2: usdhc2grp {
> + fsl,pins = <
> + IMX95_PAD_SD2_CLK__USDHC2_CLK 0x158e
> + IMX95_PAD_SD2_CMD__USDHC2_CMD 0x138e
> + IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x138e
> + IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x138e
> + IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x138e
> + IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x138e
> + IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
> + >;
> + };
> +
> + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
> + fsl,pins = <
> + IMX95_PAD_SD2_CLK__USDHC2_CLK 0x158e
> + IMX95_PAD_SD2_CMD__USDHC2_CMD 0x138e
> + IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x138e
> + IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x138e
> + IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x138e
> + IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x138e
> + IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
> + >;
> + };
> +
> + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
> + fsl,pins = <
> + IMX95_PAD_SD2_CLK__USDHC2_CLK 0x15fe
> + IMX95_PAD_SD2_CMD__USDHC2_CMD 0x13fe
> + IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x13fe
> + IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x13fe
> + IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x13fe
> + IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x13fe
> + IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
> + >;
> + };
> +};
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 7+ messages in thread* Re: [PATCH v6 3/3] arm64: dts: freescale: add i.MX95 19x19 EVK minimal board dts
2024-06-05 1:22 ` [PATCH v6 3/3] arm64: dts: freescale: add i.MX95 19x19 EVK minimal board dts Peng Fan (OSS)
2024-06-05 3:34 ` Amit Singh Tomar
@ 2024-06-17 1:09 ` Shawn Guo
1 sibling, 0 replies; 7+ messages in thread
From: Shawn Guo @ 2024-06-17 1:09 UTC (permalink / raw)
To: Peng Fan (OSS)
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam, devicetree,
linux-kernel, imx, linux-arm-kernel, Alexander Stein, Peng Fan
On Wed, Jun 05, 2024 at 09:22:50AM +0800, Peng Fan (OSS) wrote:
> From: Peng Fan <peng.fan@nxp.com>
>
> Add a minimal dts for i.MX95 19x19 EVK board:
> - lpuart1 as console
> - sdhc1/2 as storage
>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> ---
> arch/arm64/boot/dts/freescale/Makefile | 1 +
> arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts | 200 ++++++++++++++++++++++
> 2 files changed, 201 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
> index 1b1e4db02071..c3fef4e4d8dd 100644
> --- a/arch/arm64/boot/dts/freescale/Makefile
> +++ b/arch/arm64/boot/dts/freescale/Makefile
> @@ -239,6 +239,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx93-phyboard-segin.dtb
> dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba93xxca.dtb
> dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba93xxla.dtb
> dtb-$(CONFIG_ARCH_MXC) += imx93-var-som-symphony.dtb
> +dtb-$(CONFIG_ARCH_MXC) += imx95-19x19-evk.dtb
>
> imx8mm-venice-gw72xx-0x-imx219-dtbs := imx8mm-venice-gw72xx-0x.dtb imx8mm-venice-gw72xx-0x-imx219.dtbo
> imx8mm-venice-gw72xx-0x-rpidsi-dtbs := imx8mm-venice-gw72xx-0x.dtb imx8mm-venice-gw72xx-0x-rpidsi.dtbo
> diff --git a/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts b/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts
> new file mode 100644
> index 000000000000..2c2f3cfbe11a
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts
> @@ -0,0 +1,200 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright 2024 NXP
> + */
> +
> +/dts-v1/;
> +
> +#include "imx95.dtsi"
> +
> +/ {
> + model = "NXP i.MX95 19X19 board";
> + compatible = "fsl,imx95-19x19-evk", "fsl,imx95";
> +
> + aliases {
> + mmc0 = &usdhc1;
> + mmc1 = &usdhc2;
> + serial0 = &lpuart1;
> + };
> +
> + chosen {
> + stdout-path = &lpuart1;
> + };
> +
> + memory@80000000 {
> + device_type = "memory";
> + reg = <0x0 0x80000000 0 0x80000000>;
> + };
> +
> + reserved-memory {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + linux_cma: linux,cma {
> + compatible = "shared-dma-pool";
> + alloc-ranges = <0 0x80000000 0 0x7F000000>;
> + size = <0 0x3c000000>;
> + linux,cma-default;
> + reusable;
> + };
> + };
> +
> + reg_usdhc2_vmmc: regulator-usdhc2 {
> + compatible = "regulator-fixed";
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
> + regulator-name = "VDD_SD2_3V3";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>;
> + off-on-delay-us = <12000>;
> + enable-active-high;
enable-active-high right after line of gpio = <... GPIO_ACTIVE_HIGH>;
Shawn
> + };
> +};
> +
> +&lpuart1 {
> + /* console */
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_uart1>;
> + status = "okay";
> +};
> +
> +&mu7 {
> + status = "okay";
> +};
> +
> +&usdhc1 {
> + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
> + pinctrl-0 = <&pinctrl_usdhc1>;
> + pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
> + pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
> + pinctrl-3 = <&pinctrl_usdhc1>;
> + bus-width = <8>;
> + non-removable;
> + no-sdio;
> + no-sd;
> + status = "okay";
> +};
> +
> +&usdhc2 {
> + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
> + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
> + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
> + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
> + pinctrl-3 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
> + cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
> + vmmc-supply = <®_usdhc2_vmmc>;
> + bus-width = <4>;
> + status = "okay";
> +};
> +
> +&wdog3 {
> + fsl,ext-reset-output;
> + status = "okay";
> +};
> +
> +&scmi_iomuxc {
> + pinctrl_uart1: uart1grp {
> + fsl,pins = <
> + IMX95_PAD_UART1_RXD__AONMIX_TOP_LPUART1_RX 0x31e
> + IMX95_PAD_UART1_TXD__AONMIX_TOP_LPUART1_TX 0x31e
> + >;
> + };
> +
> + pinctrl_usdhc1: usdhc1grp {
> + fsl,pins = <
> + IMX95_PAD_SD1_CLK__USDHC1_CLK 0x158e
> + IMX95_PAD_SD1_CMD__USDHC1_CMD 0x138e
> + IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x138e
> + IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x138e
> + IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x138e
> + IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x138e
> + IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x138e
> + IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x138e
> + IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x138e
> + IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x138e
> + IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x158e
> + >;
> + };
> +
> + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
> + fsl,pins = <
> + IMX95_PAD_SD1_CLK__USDHC1_CLK 0x158e
> + IMX95_PAD_SD1_CMD__USDHC1_CMD 0x138e
> + IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x138e
> + IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x138e
> + IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x138e
> + IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x138e
> + IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x138e
> + IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x138e
> + IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x138e
> + IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x138e
> + IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x158e
> + >;
> + };
> +
> + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
> + fsl,pins = <
> + IMX95_PAD_SD1_CLK__USDHC1_CLK 0x15fe
> + IMX95_PAD_SD1_CMD__USDHC1_CMD 0x13fe
> + IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe
> + IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe
> + IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe
> + IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe
> + IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe
> + IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe
> + IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe
> + IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe
> + IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe
> + >;
> + };
> +
> + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
> + fsl,pins = <
> + IMX95_PAD_SD2_RESET_B__GPIO3_IO_BIT7 0x31e
> + >;
> + };
> +
> + pinctrl_usdhc2_gpio: usdhc2gpiogrp {
> + fsl,pins = <
> + IMX95_PAD_SD2_CD_B__GPIO3_IO_BIT0 0x31e
> + >;
> + };
> +
> + pinctrl_usdhc2: usdhc2grp {
> + fsl,pins = <
> + IMX95_PAD_SD2_CLK__USDHC2_CLK 0x158e
> + IMX95_PAD_SD2_CMD__USDHC2_CMD 0x138e
> + IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x138e
> + IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x138e
> + IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x138e
> + IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x138e
> + IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
> + >;
> + };
> +
> + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
> + fsl,pins = <
> + IMX95_PAD_SD2_CLK__USDHC2_CLK 0x158e
> + IMX95_PAD_SD2_CMD__USDHC2_CMD 0x138e
> + IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x138e
> + IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x138e
> + IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x138e
> + IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x138e
> + IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
> + >;
> + };
> +
> + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
> + fsl,pins = <
> + IMX95_PAD_SD2_CLK__USDHC2_CLK 0x15fe
> + IMX95_PAD_SD2_CMD__USDHC2_CMD 0x13fe
> + IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x13fe
> + IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x13fe
> + IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x13fe
> + IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x13fe
> + IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
> + >;
> + };
> +};
>
> --
> 2.37.1
>
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v6 0/3] arm64: dts: add i.MX95 and EVK board
2024-06-05 1:22 [PATCH v6 0/3] arm64: dts: add i.MX95 and EVK board Peng Fan (OSS)
2024-06-05 1:22 ` [PATCH v6 1/3] dt-bindings: arm: fsl: add i.MX95 19x19 " Peng Fan (OSS)
2024-06-05 1:22 ` [PATCH v6 3/3] arm64: dts: freescale: add i.MX95 19x19 EVK minimal board dts Peng Fan (OSS)
@ 2024-06-05 13:11 ` Rob Herring (Arm)
2024-06-11 3:32 ` Peng Fan
2 siblings, 1 reply; 7+ messages in thread
From: Rob Herring (Arm) @ 2024-06-05 13:11 UTC (permalink / raw)
To: Peng Fan (OSS)
Cc: Conor Dooley, linux-arm-kernel, Alexander Stein, Peng Fan,
Fabio Estevam, linux-kernel, Sascha Hauer, Krzysztof Kozlowski,
Shawn Guo, Conor Dooley, imx, Pengutronix Kernel Team, devicetree
On Wed, 05 Jun 2024 09:22:47 +0800, Peng Fan (OSS) wrote:
> Add a minimal i.MX95 dtsi and EVK board dts.
> i.MX95 has a M33 running SCMI firmware that supports
> pinctrl/power/perf/clock and etc.
>
> imx95-pinfunc.h will trigger checkpatch error, that is expected and same
> as other i.MX platforms.
>
> In v6, I added back a dependency on pinctrl, because [1] has got A-b/R-b
> from Maintainers, so it would be soon got merged.
>
> There will be dtbs_check error before [1] got landed. With [1] merged,
> there will be no dtbs_check error.
>
> [1] https://lore.kernel.org/all/20240521-pinctrl-scmi-imx95-v1-0-9a1175d735fd@nxp.com/
>
> This patchset is just a minimal support for i.MX95. After this patchset
> is accepted, a following patchset will include more nodes and features.
>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> ---
> Changes in v6:
> - Add pinctrl nodes and pin settings
> - Add imx95-pinfunc.h
> - Drop fsl,cd-gpio-disable-wakeup which is downstream property
> - Per i.MX M33 SCMI firmware, drop unused PERF entries in imx95-power.h
> - Rebased to next-20240604
> - Link to v5: https://lore.kernel.org/r/20240506-imx95-dts-v3-v5-0-5ec9b99cfb2f@nxp.com
>
> Changes in v5:
> - Drop unused regulator and alias for now.
> - Fix CHECK_DTB warning.
> - Link to v4: https://lore.kernel.org/r/20240503-imx95-dts-v3-v4-0-535ddc2bde73@nxp.com
>
> Changes in v4:
> - Sort nodes by address
> - Drop coresight nodes
> - Align clock rates for SDHC1-3
> - Drop wdog3 board specific property
> - Link to v3: https://lore.kernel.org/r/20240428-imx95-dts-v3-v3-0-765395f88b9f@nxp.com
>
> Changes in v3:
> - Drop irqsteer node because binding not accepted
> - Pass dtbs_check
> - Link to v2: https://lore.kernel.org/r/20240226-imx95-dts-v2-0-00e36637b07e@nxp.com
>
> Changes in v2:
> - Addressed Rob and Krzysztof's comments, and fix dts_check issue
> To pass the dtbs_check, need apply:
> https://lore.kernel.org/all/20240226070910.3379108-1-peng.fan@oss.nxp.com/
> https://lore.kernel.org/all/20240226130243.3820915-1-peng.fan@oss.nxp.com/
> https://lore.kernel.org/all/20240226130516.3821803-1-peng.fan@oss.nxp.com/
> https://lore.kernel.org/all/20240226130826.3824251-1-peng.fan@oss.nxp.com/
> https://lore.kernel.org/all/20240219-imx-mailbox-v8-1-75535a87794e@nxp.com/
>
> - Link to v1: https://lore.kernel.org/r/20240218-imx95-dts-v1-0-2959f89f2018@nxp.com
>
> ---
> Peng Fan (3):
> dt-bindings: arm: fsl: add i.MX95 19x19 EVK board
> arm64: dts: freescale: add i.MX95 basic dtsi
> arm64: dts: freescale: add i.MX95 19x19 EVK minimal board dts
>
> Documentation/devicetree/bindings/arm/fsl.yaml | 6 +
> arch/arm64/boot/dts/freescale/Makefile | 1 +
> arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts | 200 ++++
> arch/arm64/boot/dts/freescale/imx95-clock.h | 187 ++++
> arch/arm64/boot/dts/freescale/imx95-pinfunc.h | 865 +++++++++++++++++
> arch/arm64/boot/dts/freescale/imx95-power.h | 47 +
> arch/arm64/boot/dts/freescale/imx95.dtsi | 1063 +++++++++++++++++++++
> 7 files changed, 2369 insertions(+)
> ---
> base-commit: a1bede4830147a5a29ea6443724837ee0b126fd9
> change-id: 20240428-imx95-dts-v3-bee59f0e559b
>
> Best regards,
> --
> Peng Fan <peng.fan@nxp.com>
>
>
>
My bot found new DTB warnings on the .dts files added or changed in this
series.
Some warnings may be from an existing SoC .dtsi. Or perhaps the warnings
are fixed by another series. Ultimately, it is up to the platform
maintainer whether these warnings are acceptable or not. No need to reply
unless the platform maintainer has comments.
If you already ran DT checks and didn't see these error(s), then
make sure dt-schema is up to date:
pip3 install dtschema --upgrade
New warnings running 'make CHECK_DTBS=y freescale/imx95-19x19-evk.dtb' for 20240605-imx95-dts-v3-v6-0-2ce275ed0e80@nxp.com:
arch/arm64/boot/dts/freescale/imx95-19x19-evk.dtb: scmi: protocol@19: Unevaluated properties are not allowed ('regusdhc2vmmcgrp', 'uart1grp', 'usdhc1-100mhzgrp', 'usdhc1-200mhzgrp', 'usdhc1grp', 'usdhc2-100mhzgrp', 'usdhc2-200mhzgrp', 'usdhc2gpiogrp', 'usdhc2grp' were unexpected)
from schema $id: http://devicetree.org/schemas/firmware/arm,scmi.yaml#
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 7+ messages in thread* RE: [PATCH v6 0/3] arm64: dts: add i.MX95 and EVK board
2024-06-05 13:11 ` [PATCH v6 0/3] arm64: dts: add i.MX95 and EVK board Rob Herring (Arm)
@ 2024-06-11 3:32 ` Peng Fan
0 siblings, 0 replies; 7+ messages in thread
From: Peng Fan @ 2024-06-11 3:32 UTC (permalink / raw)
To: Rob Herring (Arm), Peng Fan (OSS)
Cc: Conor Dooley, linux-arm-kernel@lists.infradead.org,
Alexander Stein, Fabio Estevam, linux-kernel@vger.kernel.org,
Sascha Hauer, Krzysztof Kozlowski, Shawn Guo, Conor Dooley,
imx@lists.linux.dev, Pengutronix Kernel Team,
devicetree@vger.kernel.org
Hi Rob, Shawn
> Subject: Re: [PATCH v6 0/3] arm64: dts: add i.MX95 and EVK board
>
>
> On Wed, 05 Jun 2024 09:22:47 +0800, Peng Fan (OSS) wrote:
> > Add a minimal i.MX95 dtsi and EVK board dts.
> > i.MX95 has a M33 running SCMI firmware that supports
> > pinctrl/power/perf/clock and etc.
> >
> > imx95-pinfunc.h will trigger checkpatch error, that is expected and
> > same as other i.MX platforms.
> >
> > In v6, I added back a dependency on pinctrl, because [1] has got
> > A-b/R-b from Maintainers, so it would be soon got merged.
> >
> > There will be dtbs_check error before [1] got landed. With [1] merged,
> > there will be no dtbs_check error.
> >
....
> >
> >
> >
>
>
> My bot found new DTB warnings on the .dts files added or changed in this
> series.
>
> Some warnings may be from an existing SoC .dtsi. Or perhaps the warnings
> are fixed by another series. Ultimately, it is up to the platform maintainer
> whether these warnings are acceptable or not. No need to reply unless the
> platform maintainer has comments.
>
> If you already ran DT checks and didn't see these error(s), then make sure dt-
> schema is up to date:
>
> pip3 install dtschema --upgrade
>
>
> New warnings running 'make CHECK_DTBS=y freescale/imx95-19x19-evk.dtb'
> for 20240605-imx95-dts-v3-v6-0-2ce275ed0e80@nxp.com:
>
> arch/arm64/boot/dts/freescale/imx95-19x19-evk.dtb: scmi: protocol@19:
> Unevaluated properties are not allowed ('regusdhc2vmmcgrp', 'uart1grp',
> 'usdhc1-100mhzgrp', 'usdhc1-200mhzgrp', 'usdhc1grp', 'usdhc2-100mhzgrp',
> 'usdhc2-200mhzgrp', 'usdhc2gpiogrp', 'usdhc2grp' were unexpected)
> from schema $id:
Since Linus has applied the pinctrl patchset[1], the check will pass.
[1] https://lore.kernel.org/all/CACRpkdbpL=HUXj0hFAo+JNki_R
A9aix2sW1cg13g9=89d93PZw@mail.gmail.com/
Shawn,
In patch 3, there is one minor comment, do you expect me to send v7
or you could help update it?
Thanks,
Peng.
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