From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 25070C2BD09 for ; Wed, 3 Jul 2024 14:39:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: Content-Type:MIME-Version:References:In-Reply-To:Message-Id:Date:Subject:Cc: To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=nGcFQCOoq7VNzcpqzKxtaEpLkrw99RNp85hTA15zHKE=; b=r2OwUZJ/amfyYwOpuwPoIHLiyC 4N+iFMyGxglKlCt8huLQPJqwIIRL3HWl0CvgnmWtH9Xwzfd0LEWdiiqx0RxEat0TIB2HTPjOkdEeW mdtkMoizSzeHr3wlnq8o46WEND7IRITKBrYHtdpyO6CRiTRLD0XW9AmukDID4KYwej1p31O6TJlF2 HyV1IOihtlzyFhZWZ0V0sm1sMcJ0Ie04GMZo9v4k6xo/zeEWRlwcrTuJOeOCK5loL86XhASb6d2zK z8QL28GPU8NIRAn0S5lXyKY4pCfMZGEuyZB6vbDp1Z6R2Ji/WmtQGutkJnD8apcoWpYdtlPbVaqC7 loSYaThQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sP18h-0000000AVVd-3nAQ; Wed, 03 Jul 2024 14:39:19 +0000 Received: from dfw.source.kernel.org ([2604:1380:4641:c500::1]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1sP18H-0000000AVIB-3O9H for linux-arm-kernel@lists.infradead.org; Wed, 03 Jul 2024 14:38:55 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by dfw.source.kernel.org (Postfix) with ESMTP id 28A1762285; Wed, 3 Jul 2024 14:38:53 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id C0E6AC2BD10; Wed, 3 Jul 2024 14:38:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1720017532; bh=MLzXW0zmt8TQcHGK5nYiqQdxT5V+dSydfz7v2Sdsn+Y=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=UvzXEd+OvZE0GLMzyCnlChXUeaWhWzEJj3t77gcq+UEcXMBtRoDIphusBsCr6EWNK cb6ncbDUbZ8yHOyZ1ge01dmAPU4OSt0ItHtzAlU18+IIYgDmn21DivLA65n8M8hSXZ 4mAd0279LkOIYcnzbu7cxmzpNPZb5n+Ug0yVV++BH5+DxmgS+NUkXPCKL5Fs+cxutr +LvJsAIDn9ruMwtdpXAN1u2eO/8Mt6HJAQ6Yj0a4YrQQmnD+8ZHh7kkEBnGGIDFuB0 dfxJEqm3lzV0s9vcNfBtfAD+IaUCmE5S42Puaf2B0VK3HhupOxtVWkunkRKjlZvLtW GqGKYB49MONug== From: Will Deacon To: Russell King , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , Marc Zyngier , Oliver Upton , James Morse , Suzuki K Poulose , Zenghui Yu , Catalin Marinas , James Clark , "Rob Herring (Arm)" Cc: kernel-team@android.com, Will Deacon , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, kvmarm@lists.linux.dev Subject: Re: [PATCH v2 00/12] arm64: Add support for Armv9.4 PMU fixed instruction counter Date: Wed, 3 Jul 2024 15:38:44 +0100 Message-Id: <172001203729.3396033.17013529444643308853.b4-ty@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20240626-arm-pmu-3-9-icntr-v2-0-c9784b4f4065@kernel.org> References: <20240626-arm-pmu-3-9-icntr-v2-0-c9784b4f4065@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240703_073853_968262_6233527E X-CRM114-Status: GOOD ( 12.47 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, 26 Jun 2024 16:32:24 -0600, Rob Herring (Arm) wrote: > This series adds support for the optional fixed instruction counter > added in Armv9.4 PMU. Most of the series is a refactoring to remove the > index to counter number conversion which dates back to the Armv7 PMU > driver. Removing it is necessary in order to support more than 32 > counters without a bunch of conditional code further complicating the > conversion. > > [...] Applied to will (for-next/perf), thanks! [01/12] perf: arm_pmuv3: Avoid assigning fixed cycle counter with threshold https://git.kernel.org/will/c/81e15ca3e523 [02/12] perf: arm_pmuv3: Drop unnecessary IS_ENABLED(CONFIG_ARM64) check https://git.kernel.org/will/c/598c1a2d9f4b [03/12] perf/arm: Move 32-bit PMU drivers to drivers/perf/ https://git.kernel.org/will/c/8d75537bebfa [04/12] perf: arm_v6/7_pmu: Drop non-DT probe support https://git.kernel.org/will/c/12f051c987dc [05/12] perf: arm_pmuv3: Include asm/arm_pmuv3.h from linux/perf/arm_pmuv3.h https://git.kernel.org/will/c/d688ffa26942 [06/12] perf: arm_pmu: Remove event index to counter remapping https://git.kernel.org/will/c/b7e89b0f5bd7 [07/12] perf: arm_pmuv3: Prepare for more than 32 counters https://git.kernel.org/will/c/12fef9fb7179 [08/12] KVM: arm64: pmu: Use arm_pmuv3.h register accessors https://git.kernel.org/will/c/6ef2846c17a3 [09/12] KVM: arm64: pmu: Use generated define for PMSELR_EL0.SEL access https://git.kernel.org/will/c/558fdd12c069 [10/12] arm64: perf/kvm: Use a common PMU cycle counter define https://git.kernel.org/will/c/323bc9e17c01 [11/12] KVM: arm64: Refine PMU defines for number of counters https://git.kernel.org/will/c/be884dd62461 [12/12] perf: arm_pmuv3: Add support for Armv9.4 PMU instruction counter https://git.kernel.org/will/c/dc4c33f753ca Cheers, -- Will https://fixes.arm64.dev https://next.arm64.dev https://will.arm64.dev