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Mon, 13 Apr 2020 08:25:31 -0000 (UTC) Received: by smtp.codeaurora.org (Postfix, from userid 1001) id 4556FC43636; Mon, 13 Apr 2020 08:25:31 +0000 (UTC) Received: from mail.codeaurora.org (localhost.localdomain [127.0.0.1]) (using TLSv1 with cipher ECDHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) (Authenticated sender: saiprakash.ranjan) by smtp.codeaurora.org (Postfix) with ESMTPSA id 93F84C433F2; Mon, 13 Apr 2020 08:25:30 +0000 (UTC) MIME-Version: 1.0 Date: Mon, 13 Apr 2020 13:55:30 +0530 From: Sai Prakash Ranjan To: Suzuki K Poulose Subject: Re: [PATCH] coresight: tmc: Read TMC mode only when TMC hw is enabled In-Reply-To: <9a792e3e-5a17-156d-4b59-4a3ec8f9993e@arm.com> References: <20200409113538.5008-1-saiprakash.ranjan@codeaurora.org> <9a792e3e-5a17-156d-4b59-4a3ec8f9993e@arm.com> Message-ID: <1751aeabd22bee18d2eef0f643883265@codeaurora.org> X-Sender: saiprakash.ranjan@codeaurora.org User-Agent: Roundcube Webmail/1.3.9 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200413_012539_821521_1EA7879D X-CRM114-Status: GOOD ( 19.89 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mathieu.poirier@linaro.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, swboyd@chromium.org, linux-arm-kernel@lists.infradead.org, mike.leach@linaro.org Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Suzuki, On 2020-04-13 04:47, Suzuki K Poulose wrote: > Hi Sai, > > On 04/09/2020 12:35 PM, Sai Prakash Ranjan wrote: >> Reading TMC mode register in tmc_read_prepare_etb without >> enabling the TMC hardware leads to async exceptions like >> the one in the call trace below. This can happen if the >> user tries to read the TMC etf data via device node without >> setting up source and the sink first which enables the TMC >> hardware in the path. So make sure that the TMC is enabled >> before we try to read TMC data. > > So, one can trigger the same SError by simply : > > $ cat /sys/bus/coresight/device/tmc_etb0/mgmt/mode > I do not see any SError when I run the above command. localhost ~ # cat /sys/bus/coresight/devices/tmc_etf0/mgmt/mode 0x0 And this is most likely due to commit cd9e3474bb793dc ("coresight: add PM runtime calls to coresight_simple_func()") > And also : > >> >> Kernel panic - not syncing: Asynchronous SError Interrupt >> CPU: 7 PID: 2605 Comm: hexdump Tainted: G S 5.4.30 >> #122 >> Call trace: >> dump_backtrace+0x0/0x188 >> show_stack+0x20/0x2c >> dump_stack+0xdc/0x144 >> panic+0x168/0x36c >> panic+0x0/0x36c >> arm64_serror_panic+0x78/0x84 >> do_serror+0x130/0x138 >> el1_error+0x84/0xf8 >> tmc_read_prepare_etb+0x88/0xb8 >> tmc_open+0x40/0xd8 >> misc_open+0x120/0x158 >> chrdev_open+0xb8/0x1a4 >> do_dentry_open+0x268/0x3a0 >> vfs_open+0x34/0x40 >> path_openat+0x39c/0xdf4 >> do_filp_open+0x90/0x10c >> do_sys_open+0x150/0x3e8 >> __arm64_compat_sys_openat+0x28/0x34 >> el0_svc_common+0xa8/0x160 >> el0_svc_compat_handler+0x2c/0x38 >> el0_svc_compat+0x8/0x10 >> >> Fixes: 4525412a5046 ("coresight: tmc: making prepare/unprepare >> functions generic") >> Reported-by: Stephen Boyd >> Signed-off-by: Sai Prakash Ranjan >> --- >> drivers/hwtracing/coresight/coresight-tmc.c | 5 +++++ >> drivers/hwtracing/coresight/coresight-tmc.h | 1 + >> 2 files changed, 6 insertions(+) >> >> diff --git a/drivers/hwtracing/coresight/coresight-tmc.c >> b/drivers/hwtracing/coresight/coresight-tmc.c >> index 1cf82fa58289..7bae69748ab7 100644 >> --- a/drivers/hwtracing/coresight/coresight-tmc.c >> +++ b/drivers/hwtracing/coresight/coresight-tmc.c >> @@ -62,11 +62,13 @@ void tmc_flush_and_stop(struct tmc_drvdata >> *drvdata) >> void tmc_enable_hw(struct tmc_drvdata *drvdata) >> { >> + drvdata->enable = true; >> writel_relaxed(TMC_CTL_CAPT_EN, drvdata->base + TMC_CTL); >> } >> void tmc_disable_hw(struct tmc_drvdata *drvdata) >> { >> + drvdata->enable = false; >> writel_relaxed(0x0, drvdata->base + TMC_CTL); >> } >> @@ -102,6 +104,9 @@ static int tmc_read_prepare(struct tmc_drvdata >> *drvdata) >> { >> int ret = 0; >> + if (!drvdata->enable) >> + return -EINVAL; >> + > > Does this check always guarantee that the TMC is enabled when > we actually get to reading the MODE ? This needs to be done > under the spinlock. > Ok I will make this change. Thanks, Sai -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel