From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 52606C7EE29 for ; Wed, 7 Jun 2023 09:18:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:From:References:To:Subject: CC:MIME-Version:Date:Message-ID:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=MFLj4Jo/+VJi8L/f4GMFwa6lSSAzG+SppESYsH6BD4Y=; b=yMRbvs5ussJkGX 7nVk2dRB6wmqGf4YaMFKv2/cVB08SfiJLZtXsxBcXGrSicyVKFQ9Hj5PMp3qKVvdWuEIG8Py/AwL8 Ao1KDQ2QOn5Wxm3rErVYsRJ5yuQLgj84vcupW6q4Ya0YDHFkx+W5vrWoMDicvSax5cYs+tkNK5JmM UOYR7m8cWbceVseYtS0OWL9QIX/iQI9OAYAmK3T0bgYNK0jCM74ZNak8jbrr/++ufazZ4zVNUPjhj BWXq6ApiepIy1LowgNCY1aY9QUvY9MGRhBsi7kpduD12AzPeby8Co1Xow3cu2bO2osvQ8EFJOBfjG CQ6LPeJgiaCW91/AkK+w==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1q6pJ1-005CT9-29; Wed, 07 Jun 2023 09:18:15 +0000 Received: from lelv0142.ext.ti.com ([198.47.23.249]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1q6pIy-005CRw-0Y for linux-arm-kernel@lists.infradead.org; Wed, 07 Jun 2023 09:18:14 +0000 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 3579HwtQ011001; Wed, 7 Jun 2023 04:17:58 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1686129478; bh=cnThIi8M92Ytp1qseMZ2eGmcOg2pipTSj99AMPH+Msg=; h=Date:CC:Subject:To:References:From:In-Reply-To; b=XxjdYhZYfKscd+ZonOtSsC08gUHBnhQEZc4SAm/+qIvTkAA38Bue3Zn3aWp6ZvLO7 fZYExSLZBZvIKr+MJBOL7oFrGbpWsBwx0PPxSCYP2kjqNAUPqqhx511l7Gixag8VqY 2crW8nlrC2rX1CwbzoDqAX4SeuqectAE5sW7ZIzU= Received: from DFLE106.ent.ti.com (dfle106.ent.ti.com [10.64.6.27]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 3579Hw6q041607 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 7 Jun 2023 04:17:58 -0500 Received: from DFLE108.ent.ti.com (10.64.6.29) by DFLE106.ent.ti.com (10.64.6.27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Wed, 7 Jun 2023 04:17:58 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DFLE108.ent.ti.com (10.64.6.29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Wed, 7 Jun 2023 04:17:58 -0500 Received: from [172.24.145.61] (ileaxei01-snat.itg.ti.com [10.180.69.5]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 3579HrWR069713; Wed, 7 Jun 2023 04:17:54 -0500 Message-ID: <17637227-e3c0-9cf3-5d9a-dee95a76bbf1@ti.com> Date: Wed, 7 Jun 2023 14:47:53 +0530 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.11.0 CC: , , , , , , , , , , , , Subject: Re: [PATCH v2] PCI: cadence: Fix Gen2 Link Retraining process To: Bjorn Helgaas References: <20230606162047.GA1127846@bhelgaas> Content-Language: en-US From: Siddharth Vadapalli In-Reply-To: <20230606162047.GA1127846@bhelgaas> X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230607_021812_295397_F64119F9 X-CRM114-Status: GOOD ( 30.88 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hello Bjorn, On 06/06/23 21:50, Bjorn Helgaas wrote: > On Wed, May 10, 2023 at 06:47:46PM +0530, Siddharth Vadapalli wrote: >> On 09-05-2023 23:54, Bjorn Helgaas wrote: >>> On Tue, May 09, 2023 at 12:37:31PM +0530, Siddharth Vadapalli wrote: >>>> On 09/05/23 02:44, Bjorn Helgaas wrote: >>>>> On Wed, Mar 15, 2023 at 12:38:00PM +0530, Siddharth Vadapalli wrote: >>>>>> The Link Retraining process is initiated to account for the Gen2 defect in >>>>>> the Cadence PCIe controller in J721E SoC. The errata corresponding to this >>>>>> is i2085, documented at: >>>>>> https://www.ti.com/lit/er/sprz455c/sprz455c.pdf >>>>>> >>>>>> The existing workaround implemented for the errata waits for the Data Link >>>>>> initialization to complete and assumes that the link retraining process >>>>>> at the Physical Layer has completed. However, it is possible that the >>>>>> Physical Layer training might be ongoing as indicated by the >>>>>> PCI_EXP_LNKSTA_LT bit in the PCI_EXP_LNKSTA register. >>>>>> >>>>>> Fix the existing workaround, to ensure that the Physical Layer training >>>>>> has also completed, in addition to the Data Link initialization. >>>>>> >>>>>> Fixes: 4740b969aaf5 ("PCI: cadence: Retrain Link to work around Gen2 training defect") >>>>>> Signed-off-by: Siddharth Vadapalli >>>>>> Reviewed-by: Vignesh Raghavendra >>>>>> --- >>>>>> Changes from v1: >>>>>> 1. Collect Reviewed-by tag from Vignesh Raghavendra. >>>>>> 2. Rebase on next-20230315. >>>>>> >>>>>> v1: >>>>>> https://lore.kernel.org/r/20230102075656.260333-1-s-vadapalli@ti.com >>>>>> >>>>>> .../controller/cadence/pcie-cadence-host.c | 27 +++++++++++++++++++ >>>>>> 1 file changed, 27 insertions(+) >>>>>> >>>>>> diff --git a/drivers/pci/controller/cadence/pcie-cadence-host.c b/drivers/pci/controller/cadence/pcie-cadence-host.c >>>>>> index 940c7dd701d6..5b14f7ee3c79 100644 >>>>>> --- a/drivers/pci/controller/cadence/pcie-cadence-host.c >>>>>> +++ b/drivers/pci/controller/cadence/pcie-cadence-host.c >>>>>> @@ -12,6 +12,8 @@ >>>>>> >>>>>> #include "pcie-cadence.h" >>>>>> >>>>>> +#define LINK_RETRAIN_TIMEOUT HZ >>>>>> + >>>>>> static u64 bar_max_size[] = { >>>>>> [RP_BAR0] = _ULL(128 * SZ_2G), >>>>>> [RP_BAR1] = SZ_2G, >>>>>> @@ -77,6 +79,27 @@ static struct pci_ops cdns_pcie_host_ops = { >>>>>> .write = pci_generic_config_write, >>>>>> }; >>>>>> >>>>>> +static int cdns_pcie_host_training_complete(struct cdns_pcie *pcie) >>>>> >>>>> This is kind of weird because it's named like a predicate, i.e., "this >>>>> function tells me whether link training is complete", but it returns >>>>> *zero* for success. >>>>> >>>>> This is the opposite of j721e_pcie_link_up(), which returns "true" >>>>> when the link is up, so code like this reads naturally: >>>>> >>>>> if (pcie->ops->link_up(pcie)) >>>>> /* do something if the link is up */ >>>> >>>> I agree. The function name can be changed to indicate that it is >>>> waiting for completion rather than indicating completion. If this is >>>> the only change, I will post a patch to fix it. On the other hand, >>>> based on your comments in the next section, I am thinking of an >>>> alternative approach of merging the current >>>> "cdns_pcie_host_training_complete()" function's operation as well >>>> into the "cdns_pcie_host_wait_for_link()" function. If this is >>>> acceptable, I will post a different patch and the name change patch >>>> won't be necessary. >>> >>> Yeah, sorry, I meant to delete this part of my response after I wrote >>> the one below. >>> >>>>>> @@ -118,6 +141,10 @@ static int cdns_pcie_retrain(struct cdns_pcie *pcie) >>>>>> cdns_pcie_rp_writew(pcie, pcie_cap_off + PCI_EXP_LNKCTL, >>>>>> lnk_ctl); >>>>>> >>>>>> + ret = cdns_pcie_host_training_complete(pcie); >>>>>> + if (ret) >>>>>> + return ret; >>>>>> + >>>>>> ret = cdns_pcie_host_wait_for_link(pcie); >>>>> >>>>> It seems a little clumsy that we wait for two things in succession: >>>>> >>>>> - cdns_pcie_host_training_complete() waits up to 1s for >>>>> PCI_EXP_LNKSTA_LT to be cleared >>>>> >>>>> - cdns_pcie_host_wait_for_link() waits between .9s and 1s for >>>>> LINK_UP_DL_COMPLETED on j721e (and not at all for other platforms) >>>> >>>> Is it acceptable to merge "cdns_pcie_host_training_complete()" into >>>> "cdns_pcie_host_wait_for_link()"? >>> >>> That's what I'm proposing. Maybe someone who is more familiar with >>> Cadence would have an argument against it, but I think making it >>> structurally the same as dw_pcie_wait_for_link() would be a good >>> thing. >> >> Thank you for the confirmation. I will work on it and post a patch. > > Ping, do you still plan to do this? Lorenzo currently has the > v2 patch on his pci/controller/cadence branch [1], but I haven't > merged it into -next yet on the assumption that a new version is > coming. Sorry for the delay. I have posted the V3 patch at: https://lore.kernel.org/r/20230607091427.852473-1-s-vadapalli@ti.com/ > > Bjorn > > [1] https://git.kernel.org/pub/scm/linux/kernel/git/pci/pci.git/commit/?h=controller/cadence&id=0e12f8302369 -- Regards, Siddharth. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel