From: Stephen Boyd <sboyd@kernel.org>
To: "AngeloGioacchino Del Regno"
<angelogioacchino.delregno@collabora.com>,
"Chen-Yu Tsai" <wenst@chromium.org>,
"Chia-I Wu" <olvaffe@gmail.com>,
"Dong Aisheng" <aisheng.dong@nxp.com>,
"Laura Nao" <laura.nao@collabora.com>,
"Matthias Brugger" <matthias.bgg@gmail.com>,
"Michael Turquette" <mturquette@baylibre.com>,
"Nicolas Frattaroli" <nicolas.frattaroli@collabora.com>,
"Nícolas F. R. A. Prado" <nfraprado@collabora.com>,
"Yassine Oudjana" <y.oudjana@protonmail.com>
Cc: kernel@collabora.com, linux-clk@vger.kernel.org,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-mediatek@lists.infradead.org,
Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
Subject: Re: [PATCH RESEND v3 1/5] clk: Respect CLK_OPS_PARENT_ENABLE during recalc
Date: Thu, 22 Jan 2026 18:45:33 -0700 [thread overview]
Message-ID: <176913273374.4027.10690199843699119944@lazor> (raw)
In-Reply-To: <20251215-mtk-pll-rpm-v3-1-5afb3191e869@collabora.com>
Quoting Nicolas Frattaroli (2025-12-15 03:23:58)
> When CLK_OPS_PARENT_ENABLE was introduced, it guarded various clock
> operations, such as setting the rate or switching parents. However,
> another operation that can and often does touch actual hardware state is
> recalc_rate, which may also be affected by such a dependency.
>
> Add parent enables/disables where the recalc_rate op is called directly.
>
> Fixes: fc8726a2c021 ("clk: core: support clocks which requires parents enable (part 2)")
> Fixes: a4b3518d146f ("clk: core: support clocks which requires parents enable (part 1)")
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
> Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
> ---
Applied to clk-next
next prev parent reply other threads:[~2026-01-23 1:45 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-12-15 10:23 [PATCH RESEND v3 0/5] MediaTek PLL Refactors and Fixes Nicolas Frattaroli
2025-12-15 10:23 ` [PATCH RESEND v3 1/5] clk: Respect CLK_OPS_PARENT_ENABLE during recalc Nicolas Frattaroli
2026-01-23 1:45 ` Stephen Boyd [this message]
2026-01-27 14:55 ` Alexander Stein
2026-01-28 14:11 ` Nicolas Frattaroli
2026-01-28 14:55 ` Alexander Stein
2025-12-15 10:23 ` [PATCH RESEND v3 2/5] clk: mediatek: Refactor pll registration to pass device Nicolas Frattaroli
2026-01-23 1:45 ` Stephen Boyd
2025-12-15 10:24 ` [PATCH RESEND v3 3/5] clk: mediatek: Pass device to clk_hw_register for PLLs Nicolas Frattaroli
2026-01-23 1:45 ` Stephen Boyd
2025-12-15 10:24 ` [PATCH RESEND v3 4/5] clk: mediatek: Refactor pllfh registration to pass device Nicolas Frattaroli
2026-01-23 1:45 ` Stephen Boyd
2025-12-15 10:24 ` [PATCH RESEND v3 5/5] clk: mediatek: Add mfg_eb as parent to mt8196 mfgpll clocks Nicolas Frattaroli
2026-01-23 1:45 ` Stephen Boyd
2026-01-08 12:09 ` [PATCH RESEND v3 0/5] MediaTek PLL Refactors and Fixes AngeloGioacchino Del Regno
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