[PATCH 06/10] soc/qbman: Add ARM equivalent for flush_dcache_range()

Roy Pledge
2017-03-29T21:19:02Z

On 3/16/2017 4:08 PM, Scott Wood wrote:
> On Thu, 2017-03-16 at 00:43 +0000, Roy Pledge wrote:
>> Just wanted to follow up on this - turns out the no-map; attribute is
>> what I was missing. I now have the suggested mechanism working for ARM.
>> However when I went to test on PowePC the region wasn't being enabled
>> properly. It turns out the Kconfig in arch/powerpc doesn't define
>> HAVE_GENERIC_DMA_COHERENT so this mechanism isn't available. However I
>> added it and everything worked on my PPC board as it did on ARM.
>>
>> Does anyone know why HAVE_GENERIC_DMA_COHERENT isn't defined for
>> PowerPC? I did a quick search but didn't see previous discussion on this
>> topic.
> Probably because nothing on PPC needed it.
>
> In any case, the problems with doing this on PPC run deeper than that, as I
> pointed out in:
> https://www.spinics.net/lists/arm-kernel/msg560020.html
I just pushed out an RFC patchset that uses dma_zalloc_coherent() to
setup the memory mappings as Robin suggested. This is working in our
regressions for both PPC and ARM but I only pushed the PPC changes for
now to keep the patchset small.

Scott, I'm not clear on why you don't think this will work for PPC. I
agree there are issues with flush/invalidate in the software portal area
but this patch just deals with private memory allocations. If you don't
think this approach is valid on PPC then I'm not sure how else to
implement this in a platform generic way. I'm looking forward to your
feedback as well as Robin's and others.

Thanks - Roy
> -Scott
>
>