From: Marc Zyngier <maz@kernel.org>
To: oupton@kernel.org, joey.gouly@arm.com, suzuki.poulose@arm.com,
yuzenghui@huawei.com, catalin.marinas@arm.com, will@kernel.org,
Qiang Ma <maqianga@uniontech.com>
Cc: linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH] KVM: arm64: PMU: Preserve AArch32 counter low bits
Date: Wed, 27 May 2026 11:35:22 +0100 [thread overview]
Message-ID: <177987810338.1512096.8015208676423389883.b4-ty@kernel.org> (raw)
In-Reply-To: <20260526074640.791991-1-maqianga@uniontech.com>
On Tue, 26 May 2026 15:46:40 +0800, Qiang Ma wrote:
> AArch32 writes to PMU event counters cannot update the top 32 bits,
> even when PMUv3p5 makes the counters 64-bit. KVM therefore needs to
> preserve the existing high half and only update the low half written by
> the guest, unless the caller explicitly forces a full reset through
> PMCR.P.
>
> The current code masks @val down to the old high half before taking
> lower_32_bits(val), which means the low half is always zero. As a
> result, AArch32 writes to event counters discard the guest-provided low
> 32 bits instead of storing them.
>
> [...]
Applied to fixes, thanks!
[1/1] KVM: arm64: PMU: Preserve AArch32 counter low bits
commit: 1750ad1388e03fb27068cd1f22c9c8b4590fe936
Cheers,
M.
--
Without deviation from the norm, progress is not possible.
prev parent reply other threads:[~2026-05-27 10:35 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-26 7:46 [PATCH] KVM: arm64: PMU: Preserve AArch32 counter low bits Qiang Ma
2026-05-27 10:35 ` Marc Zyngier [this message]
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