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From: heiko@sntech.de (Heiko Stübner)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v4 09/13] ARM: dts: rockchip: add cru nodes and update device clocks to use it
Date: Sun, 22 Jun 2014 22:48:17 +0200	[thread overview]
Message-ID: <1781028.8zdXlIlntt@diego> (raw)
In-Reply-To: <1808429.dNxms7FR7U@diego>

This adds a node for the clock and reset unit on rk3188 and rk3066 SoCs and
also updates the device nodes retrieve their clocks from there, instead of
the previous gate clock nodes.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
 arch/arm/boot/dts/rk3066a.dtsi | 29 ++++++++++++++++++++---------
 arch/arm/boot/dts/rk3188.dtsi  | 18 ++++++++++++++----
 arch/arm/boot/dts/rk3xxx.dtsi  | 16 ++++++++--------
 3 files changed, 42 insertions(+), 21 deletions(-)

diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi
index 4387cfd..0b36514 100644
--- a/arch/arm/boot/dts/rk3066a.dtsi
+++ b/arch/arm/boot/dts/rk3066a.dtsi
@@ -15,6 +15,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/clock/rk3066a-cru.h>
 #include "rk3xxx.dtsi"
 #include "rk3066a-clocks.dtsi"
 
@@ -45,7 +46,7 @@
 			compatible = "snps,dw-apb-timer-osc";
 			reg = <0x20038000 0x100>;
 			interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&clk_gates1 0>, <&clk_gates7 7>;
+			clocks = <&cru SCLK_TIMER0>, <&cru PCLK_TIMER0>;
 			clock-names = "timer", "pclk";
 		};
 
@@ -53,7 +54,7 @@
 			compatible = "snps,dw-apb-timer-osc";
 			reg = <0x2003a000 0x100>;
 			interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&clk_gates1 1>, <&clk_gates7 8>;
+			clocks = <&cru SCLK_TIMER1>, <&cru PCLK_TIMER1>;
 			clock-names = "timer", "pclk";
 		};
 
@@ -61,7 +62,7 @@
 			compatible = "snps,dw-apb-timer-osc";
 			reg = <0x2000e000 0x100>;
 			interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&clk_gates1 2>, <&clk_gates7 9>;
+			clocks = <&cru SCLK_TIMER2>, <&cru PCLK_TIMER2>;
 			clock-names = "timer", "pclk";
 		};
 
@@ -78,6 +79,16 @@
 			};
 		};
 
+		cru: cru at 20000000 {
+			compatible = "rockchip,rk3066a-cru";
+			reg = <0x20000000 0x1000>;
+
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+
+			rockchip,grf = <&grf>;
+		};
+
 		pinctrl at 20008000 {
 			compatible = "rockchip,rk3066a-pinctrl";
 			rockchip,grf = <&grf>;
@@ -89,7 +100,7 @@
 				compatible = "rockchip,gpio-bank";
 				reg = <0x20034000 0x100>;
 				interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
-				clocks = <&clk_gates8 9>;
+				clocks = <&cru PCLK_GPIO0>;
 
 				gpio-controller;
 				#gpio-cells = <2>;
@@ -102,7 +113,7 @@
 				compatible = "rockchip,gpio-bank";
 				reg = <0x2003c000 0x100>;
 				interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
-				clocks = <&clk_gates8 10>;
+				clocks = <&cru PCLK_GPIO1>;
 
 				gpio-controller;
 				#gpio-cells = <2>;
@@ -115,7 +126,7 @@
 				compatible = "rockchip,gpio-bank";
 				reg = <0x2003e000 0x100>;
 				interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
-				clocks = <&clk_gates8 11>;
+				clocks = <&cru PCLK_GPIO2>;
 
 				gpio-controller;
 				#gpio-cells = <2>;
@@ -128,7 +139,7 @@
 				compatible = "rockchip,gpio-bank";
 				reg = <0x20080000 0x100>;
 				interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
-				clocks = <&clk_gates8 12>;
+				clocks = <&cru PCLK_GPIO3>;
 
 				gpio-controller;
 				#gpio-cells = <2>;
@@ -141,7 +152,7 @@
 				compatible = "rockchip,gpio-bank";
 				reg = <0x20084000 0x100>;
 				interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
-				clocks = <&clk_gates8 13>;
+				clocks = <&cru PCLK_GPIO4>;
 
 				gpio-controller;
 				#gpio-cells = <2>;
@@ -154,7 +165,7 @@
 				compatible = "rockchip,gpio-bank";
 				reg = <0x2000a000 0x100>;
 				interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
-				clocks = <&clk_gates8 15>;
+				clocks = <&cru PCLK_GPIO6>;
 
 				gpio-controller;
 				#gpio-cells = <2>;
diff --git a/arch/arm/boot/dts/rk3188.dtsi b/arch/arm/boot/dts/rk3188.dtsi
index 238c996..d77bc94 100644
--- a/arch/arm/boot/dts/rk3188.dtsi
+++ b/arch/arm/boot/dts/rk3188.dtsi
@@ -15,6 +15,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/clock/rk3188-cru.h>
 #include "rk3xxx.dtsi"
 #include "rk3188-clocks.dtsi"
 
@@ -74,6 +75,15 @@
 			};
 		};
 
+		cru: cru at 20000000 {
+			compatible = "rockchip,rk3188-cru";
+			reg = <0x20000000 0x1000>;
+			rockchip,grf = <&grf>;
+
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+		};
+
 		pinctrl at 20008000 {
 			compatible = "rockchip,rk3188-pinctrl";
 			rockchip,grf = <&grf>;
@@ -87,7 +97,7 @@
 				compatible = "rockchip,rk3188-gpio-bank0";
 				reg = <0x2000a000 0x100>;
 				interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
-				clocks = <&clk_gates8 9>;
+				clocks = <&cru PCLK_GPIO0>;
 
 				gpio-controller;
 				#gpio-cells = <2>;
@@ -100,7 +110,7 @@
 				compatible = "rockchip,gpio-bank";
 				reg = <0x2003c000 0x100>;
 				interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
-				clocks = <&clk_gates8 10>;
+				clocks = <&cru PCLK_GPIO1>;
 
 				gpio-controller;
 				#gpio-cells = <2>;
@@ -113,7 +123,7 @@
 				compatible = "rockchip,gpio-bank";
 				reg = <0x2003e000 0x100>;
 				interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
-				clocks = <&clk_gates8 11>;
+				clocks = <&cru PCLK_GPIO2>;
 
 				gpio-controller;
 				#gpio-cells = <2>;
@@ -126,7 +136,7 @@
 				compatible = "rockchip,gpio-bank";
 				reg = <0x20080000 0x100>;
 				interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
-				clocks = <&clk_gates8 12>;
+				clocks = <&cru PCLK_GPIO3>;
 
 				gpio-controller;
 				#gpio-cells = <2>;
diff --git a/arch/arm/boot/dts/rk3xxx.dtsi b/arch/arm/boot/dts/rk3xxx.dtsi
index 2adf1cc9e..b47d5fe 100644
--- a/arch/arm/boot/dts/rk3xxx.dtsi
+++ b/arch/arm/boot/dts/rk3xxx.dtsi
@@ -60,14 +60,14 @@
 			compatible = "arm,cortex-a9-global-timer";
 			reg = <0x1013c200 0x20>;
 			interrupts = <GIC_PPI 11 0x304>;
-			clocks = <&dummy150m>;
+			clocks = <&cru CORE_PERI>;
 		};
 
 		local-timer at 1013c600 {
 			compatible = "arm,cortex-a9-twd-timer";
 			reg = <0x1013c600 0x20>;
 			interrupts = <GIC_PPI 13 0x304>;
-			clocks = <&dummy150m>;
+			clocks = <&cru CORE_PERI>;
 		};
 
 		uart0: serial at 10124000 {
@@ -76,7 +76,7 @@
 			interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 			reg-shift = <2>;
 			reg-io-width = <1>;
-			clocks = <&clk_gates1 8>;
+			clocks = <&cru SCLK_UART0>;
 			status = "disabled";
 		};
 
@@ -86,7 +86,7 @@
 			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 			reg-shift = <2>;
 			reg-io-width = <1>;
-			clocks = <&clk_gates1 10>;
+			clocks = <&cru SCLK_UART1>;
 			status = "disabled";
 		};
 
@@ -96,7 +96,7 @@
 			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 			reg-shift = <2>;
 			reg-io-width = <1>;
-			clocks = <&clk_gates1 12>;
+			clocks = <&cru SCLK_UART2>;
 			status = "disabled";
 		};
 
@@ -106,7 +106,7 @@
 			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 			reg-shift = <2>;
 			reg-io-width = <1>;
-			clocks = <&clk_gates1 14>;
+			clocks = <&cru SCLK_UART3>;
 			status = "disabled";
 		};
 
@@ -117,7 +117,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 
-			clocks = <&clk_gates5 10>, <&clk_gates2 11>;
+			clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
 			clock-names = "biu", "ciu";
 
 			status = "disabled";
@@ -130,7 +130,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 
-			clocks = <&clk_gates5 11>, <&clk_gates2 13>;
+			clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>;
 			clock-names = "biu", "ciu";
 
 			status = "disabled";
-- 
1.9.0

  parent reply	other threads:[~2014-06-22 20:48 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-06-22 20:41 [PATCH v4 00/13] Clock support for rk3066,rk3188 and rk3288 Heiko Stübner
2014-06-22 20:43 ` [PATCH v4 01/13] clk: composite: support determine_rate using rate_ops->round_rate + mux_ops->set_parent Heiko Stübner
2014-06-25  7:57   ` Gabriel Fernandez
2014-06-30 22:00     ` [PATCH v4.1 " Heiko Stübner
2014-07-01  9:30     ` [PATCH v4.2 " Heiko Stübner
2014-06-22 20:43 ` [PATCH v4 02/13] clk: composite: allow read-only clocks Heiko Stübner
2014-07-01 20:46   ` Mike Turquette
2014-06-22 20:44 ` [PATCH v4 03/13] clk: rockchip: add basic infrastructure for clock branches Heiko Stübner
2014-07-01 18:45   ` Mike Turquette
2014-06-22 20:44 ` [PATCH v4 04/13] clk: rockchip: add clock type for pll clocks and pll used on rk3066 Heiko Stübner
2014-06-22 20:45 ` [PATCH v4 05/13] clk: rockchip: add reset controller Heiko Stübner
2014-06-22 20:46 ` [PATCH v4 06/13] dt-bindings: add documentation for rk3188 clock and reset unit Heiko Stübner
2014-06-22 20:47 ` [PATCH v4 07/13] clk: rockchip: add clock driver for rk3188 and rk3066 clocks Heiko Stübner
2014-06-22 20:47 ` [PATCH v4 08/13] ARM: rockchip: Select ARCH_HAS_RESET_CONTROLLER Heiko Stübner
2014-06-22 20:48 ` Heiko Stübner [this message]
2014-06-22 20:48 ` [PATCH v4 10/13] ARM: dts: rockchip: move oscillator input clock into main dtsi Heiko Stübner
2014-06-22 20:49 ` [PATCH v4 11/13] arm: dts: rockchip: remove obsolete clock gate definitions Heiko Stübner
2014-06-22 20:49 ` [PATCH v4 12/13] clk: rockchip: add clock controller for rk3288 Heiko Stübner
2014-06-22 20:50 ` [PATCH v4 13/13] dt-bindings: add documentation for rk3288 cru Heiko Stübner
2014-06-29 17:41 ` [PATCH v4 00/13] Clock support for rk3066,rk3188 and rk3288 Max Schwarz

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