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[60.250.196.139]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-84282221086sm17761731b3a.10.2026.06.08.02.46.47 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 08 Jun 2026 02:46:50 -0700 (PDT) Message-ID: <178c4511-a290-4526-9e80-2fe8291f6ed3@gmail.com> Date: Mon, 8 Jun 2026 17:46:46 +0800 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 4/5] drm/verisilicon: add Nuvoton MA35D1 DCU Lite display controller support To: Icenowy Zheng , maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, airlied@gmail.com, simona@ffwll.ch, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: ychuang3@nuvoton.com, schung@nuvoton.com, yclu4@nuvoton.com, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org References: <20260608023237.305036-1-a0987203069@gmail.com> <20260608023237.305036-5-a0987203069@gmail.com> <335c237d2636764948e629dbab0b5b747ac48fa5.camel@iscas.ac.cn> Content-Language: en-US From: Joey Lu In-Reply-To: <335c237d2636764948e629dbab0b5b747ac48fa5.camel@iscas.ac.cn> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260608_024651_663995_5CDF83D1 X-CRM114-Status: GOOD ( 25.84 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 6/8/2026 2:26 PM, Icenowy Zheng wrote: > 在 2026-06-08一的 10:32 +0800，Joey Lu写道： >> The Nuvoton MA35D1 SoC integrates a Verisilicon DCUltraLite display >> controller whose register layout differs from the DC8200 in several >> important ways: >> >> 1. No CONFIG_EX commit path: framebuffer updates use the enable (bit >> 0) >>    and reset (bit 4) bits in FB_CONFIG instead of the DC8200 staging >>    registers (FB_CONFIG_EX, FB_TOP_LEFT, FB_BOTTOM_RIGHT, >>    FB_BLEND_CONFIG, PANEL_CONFIG_EX). >> >> 2. No PANEL_START register: panel output starts when >>    PANEL_CONFIG.RUNNING is set; there is no multi-display sync start >>    register. >> >> 3. Different IRQ registers: DCUltraLite uses DISP_IRQ_STA (0x147C) / >>    DISP_IRQ_EN (0x1480) versus DC8200's TOP_IRQ_ACK (0x0010) / >>    TOP_IRQ_EN (0x0014). >> >> 4. Per-frame commit cycle: DCUltraLite requires the VALID bit in >>    FB_CONFIG to be set at the start of each atomic commit >> (crtc_begin) >>    and cleared after (crtc_flush). >> >> 5. Simpler clock topology: only 'core' (bus gate) and 'pix0' (pixel >>    divider) clocks; no axi or ahb clocks required.  Make axi_clk and >>    ahb_clk optional (devm_clk_get_optional_enabled) so DCUltraLite >>    nodes without those clocks are handled gracefully. >> >> Add vs_dcu_lite.c implementing the vs_dc_funcs vtable for the above > Nitpick: could you use vs_dc8000 to make things more aligned? (Although > I must admit that DCUltraLite is the first revision to be supported in > this codepath). Understood. I will rename `vs_dcu_lite.c` to `vs_dc8000.c`, all internal functions from `vs_dcu_lite_*` to `vs_dc8000_*`, the exported symbol from `vs_dcu_lite_funcs` to `vs_dc8000_funcs`, and update the Makefile accordingly. >> differences.  The probe now selects vs_dcu_lite_funcs when the >> identified generation is VSDC_GEN_DC8000 (DCUltraLite reads model >> 0x0, >> revision 0x5560, customer_id 0x305). >> >> Extend Kconfig to allow building on ARCH_MA35 platforms. > Maybe the Kconfig change could be in the last commit or a dedicated > commit before current ones? Because it's only meaningful after the HWDB > item is added. > > Thanks, > Icenowy Understood. The Kconfig change adding `ARCH_MA35` will be moved to a separate commit placed after the HWDB entry is added, or as the final commit in the series. >> Signed-off-by: Joey Lu >> --- >>  drivers/gpu/drm/verisilicon/Kconfig       |  2 +- >>  drivers/gpu/drm/verisilicon/Makefile      |  2 +- >>  drivers/gpu/drm/verisilicon/vs_dc.c       |  9 ++- >>  drivers/gpu/drm/verisilicon/vs_dcu_lite.c | 78 >> +++++++++++++++++++++++ >>  4 files changed, 86 insertions(+), 5 deletions(-) >>  create mode 100644 drivers/gpu/drm/verisilicon/vs_dcu_lite.c >> >> diff --git a/drivers/gpu/drm/verisilicon/Kconfig >> b/drivers/gpu/drm/verisilicon/Kconfig >> index 7cce86ec8603..295d246eb4b4 100644 >> --- a/drivers/gpu/drm/verisilicon/Kconfig >> +++ b/drivers/gpu/drm/verisilicon/Kconfig >> @@ -2,7 +2,7 @@ >>  config DRM_VERISILICON_DC >>   tristate "DRM Support for Verisilicon DC-series display >> controllers" >>   depends on DRM && COMMON_CLK >> - depends on RISCV || COMPILE_TEST >> + depends on RISCV || ARCH_MA35 || COMPILE_TEST >>   select DRM_BRIDGE_CONNECTOR >>   select DRM_CLIENT_SELECTION >>   select DRM_DISPLAY_HELPER >> diff --git a/drivers/gpu/drm/verisilicon/Makefile >> b/drivers/gpu/drm/verisilicon/Makefile >> index 9d4cd16452fa..960af0861dfa 100644 >> --- a/drivers/gpu/drm/verisilicon/Makefile >> +++ b/drivers/gpu/drm/verisilicon/Makefile >> @@ -1,6 +1,6 @@ >>  # SPDX-License-Identifier: GPL-2.0-only >> >> -verisilicon-dc-objs := vs_bridge.o vs_crtc.o vs_dc.o vs_dc8200.o >> vs_drm.o vs_hwdb.o \ >> +verisilicon-dc-objs := vs_bridge.o vs_crtc.o vs_dc.o vs_dc8200.o >> vs_dcu_lite.o vs_drm.o vs_hwdb.o \ >>   vs_plane.o vs_primary_plane.o vs_cursor_plane.o >> >>  obj-$(CONFIG_DRM_VERISILICON_DC) += verisilicon-dc.o >> diff --git a/drivers/gpu/drm/verisilicon/vs_dc.c >> b/drivers/gpu/drm/verisilicon/vs_dc.c >> index c94957024189..81a8d9bf85bd 100644 >> --- a/drivers/gpu/drm/verisilicon/vs_dc.c >> +++ b/drivers/gpu/drm/verisilicon/vs_dc.c >> @@ -90,13 +90,13 @@ static int vs_dc_probe(struct platform_device >> *pdev) >>   return PTR_ERR(dc->core_clk); >>   } >> >> - dc->axi_clk = devm_clk_get_enabled(dev, "axi"); >> + dc->axi_clk = devm_clk_get_optional_enabled(dev, "axi"); >>   if (IS_ERR(dc->axi_clk)) { >>   dev_err(dev, "can't get axi clock\n"); >>   return PTR_ERR(dc->axi_clk); >>   } >> >> - dc->ahb_clk = devm_clk_get_enabled(dev, "ahb"); >> + dc->ahb_clk = devm_clk_get_optional_enabled(dev, "ahb"); >>   if (IS_ERR(dc->ahb_clk)) { >>   dev_err(dev, "can't get ahb clock\n"); >>   return PTR_ERR(dc->ahb_clk); >> @@ -134,7 +134,10 @@ static int vs_dc_probe(struct platform_device >> *pdev) >>   dev_info(dev, "Found DC%x rev %x customer %x\n", dc- >>> identity.model, >>   dc->identity.revision, dc->identity.customer_id); >> >> - dc->funcs = &vs_dc8200_funcs; >> + if (dc->identity.generation == VSDC_GEN_DC8200) >> + dc->funcs = &vs_dc8200_funcs; >> + else >> + dc->funcs = &vs_dcu_lite_funcs; >> >>   if (port_count > dc->identity.display_count) { >>   dev_err(dev, "too many downstream ports than HW >> capability\n"); >> diff --git a/drivers/gpu/drm/verisilicon/vs_dcu_lite.c >> b/drivers/gpu/drm/verisilicon/vs_dcu_lite.c >> new file mode 100644 >> index 000000000000..11ef57d5ebaa >> --- /dev/null >> +++ b/drivers/gpu/drm/verisilicon/vs_dcu_lite.c >> @@ -0,0 +1,78 @@ >> +// SPDX-License-Identifier: GPL-2.0-only >> +/* >> + * Copyright (C) 2026 Joey Lu >> + */ >> + >> +#include >> + >> +#include "vs_crtc_regs.h" >> +#include "vs_dc.h" >> +#include "vs_primary_plane_regs.h" >> + >> +static void vs_dcu_lite_bridge_enable(struct vs_dc *dc, unsigned int >> output) >> +{ >> + regmap_set_bits(dc->regs, VSDC_FB_CONFIG(output), >> + VSDC_FB_CONFIG_RESET); >> +} >> + >> +static void vs_dcu_lite_bridge_disable(struct vs_dc *dc, unsigned >> int output) >> +{ >> + regmap_clear_bits(dc->regs, VSDC_FB_CONFIG(output), >> +   VSDC_FB_CONFIG_RESET); >> +} >> + >> +static void vs_dcu_lite_crtc_begin(struct vs_dc *dc, unsigned int >> output) >> +{ >> + regmap_set_bits(dc->regs, VSDC_FB_CONFIG(output), >> + VSDC_FB_CONFIG_VALID); >> +} >> + >> +static void vs_dcu_lite_crtc_flush(struct vs_dc *dc, unsigned int >> output) >> +{ >> + regmap_clear_bits(dc->regs, VSDC_FB_CONFIG(output), >> +   VSDC_FB_CONFIG_VALID); >> +} >> + >> +static void vs_dcu_lite_crtc_enable(struct vs_dc *dc, unsigned int >> output) >> +{ >> + regmap_set_bits(dc->regs, VSDC_FB_CONFIG(output), >> + VSDC_FB_CONFIG_ENABLE); >> +} >> + >> +static void vs_dcu_lite_crtc_disable(struct vs_dc *dc, unsigned int >> output) >> +{ >> + regmap_clear_bits(dc->regs, VSDC_FB_CONFIG(output), >> +   VSDC_FB_CONFIG_ENABLE); >> +} >> + >> +static void vs_dcu_lite_enable_vblank(struct vs_dc *dc, unsigned int >> output) >> +{ >> + regmap_set_bits(dc->regs, VSDC_DISP_IRQ_EN, >> + VSDC_DISP_IRQ_VSYNC(output)); >> +} >> + >> +static void vs_dcu_lite_disable_vblank(struct vs_dc *dc, unsigned >> int output) >> +{ >> + regmap_clear_bits(dc->regs, VSDC_DISP_IRQ_EN, >> +   VSDC_DISP_IRQ_VSYNC(output)); >> +} >> + >> +static u32 vs_dcu_lite_irq_handler(struct vs_dc *dc) >> +{ >> + u32 irqs; >> + >> + regmap_read(dc->regs, VSDC_DISP_IRQ_STA, &irqs); >> + return irqs; >> +} >> + >> +const struct vs_dc_funcs vs_dcu_lite_funcs = { >> + .bridge_enable = vs_dcu_lite_bridge_enable, >> + .bridge_disable = >> vs_dcu_lite_bridge_disable, >> + .crtc_begin = vs_dcu_lite_crtc_begin, >> + .crtc_flush = vs_dcu_lite_crtc_flush, >> + .crtc_enable = vs_dcu_lite_crtc_enable, >> + .crtc_disable = vs_dcu_lite_crtc_disable, >> + .enable_vblank = vs_dcu_lite_enable_vblank, >> + .disable_vblank = >> vs_dcu_lite_disable_vblank, >> + .irq_handler = vs_dcu_lite_irq_handler, >> +};