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Wed, 30 Sep 2026 05:11:48 -0700 (PDT) Received: from [127.0.1.1] ([92.241.26.38]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4a01771b0e8sm58527975e9.12.2026.09.30.05.11.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 30 Sep 2026 05:11:48 -0700 (PDT) From: Fil Dunsky To: Arnd Bergmann Cc: Linus Walleij , Krzysztof Kozlowski , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Greg Kroah-Hartman , Jiri Slaby , Russell King , Alexandre Belloni , Drew Fustini , Lorenzo Pieralisi , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org, Jason Li Subject: Re: [PATCH RFC 04/10] ARM: cortina: Add support for the CS75xx SoC family In-Reply-To: References: <20260930-b4-cs75xx-v1-0-4617c4463529@gmail.com> <20260930-b4-cs75xx-v1-4-4617c4463529@gmail.com> <65c87e07-1722-44c2-9a08-ed9e18902058@kernel.org> <179076583795.3054628.14443934429806440798@gmail.com> <179076863241.3327419.16233537387530771884@gmail.com> Date: Wed, 30 Sep 2026 15:11:46 +0300 Message-ID: <179077030602.3399593.12266354979192327093@gmail.com> Content-Transfer-Encoding: 8bit MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8"; format="fixed" X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260930_131150_957804_1708473E X-CRM114-Status: GOOD ( 26.62 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, Sep 30, 2026 at 02:02:43PM +0200, Arnd Bergmann wrote: > I think I would go with mach-cortina here. Or even better would be > to find a way not to need any code. If you control the boot loader, > you could just implement the psci ops there and actually bring > up the CPU from EL3. If that doesn't work, maybe it is time to > actually have a generic spin-table implementation on arm32 the > way we do on arm64. As far as I can tell, your code is just > a copy of that anyway, though we have so far never added this to > common arm32 code in order to encourage SoC vendors to use psci. The boot loader is the stock U-Boot 2009.11 from the router vendor, and replacing it on these devices is risky enough that I would rather not depend on it, so PSCI is not really an option here. A generic spin-table for arm32 would work for me, with two differences from the arm64 one that it would have to cover: the release address here is an MMIO register in the global control block, not a word in memory, so it has to be written with writel() through an ioremap(), and the Cortex-A9 SCU gets enabled in smp_prepare_cpus() (I have not checked whether the stock U-Boot already does that). If that sounds acceptable, I can post it as a separate patch in v2 and drop the enable method binding and mach directory from this series; otherwise I will keep the small platsmp.c under the name you and Linus agree on. > I don't have a strong preference either. If nobody else has a clear > guidance, changing to "cortina-access,..." would seems the most consistent > to me. OK, unless the DT maintainers object I will switch to "cortina-access," in v2. Thanks, Fil