From: stillcompiling@gmail.com (Joshua Clayton)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH fpga 2/9] fpga zynq: Check the bitstream for validity
Date: Wed, 9 Nov 2016 16:04:07 -0800 [thread overview]
Message-ID: <17912798-e55d-253f-42fc-c7287d067e00@gmail.com> (raw)
In-Reply-To: <1478732303-13718-3-git-send-email-jgunthorpe@obsidianresearch.com>
Hi Jason,
Minor comment below:
On 11/09/2016 02:58 PM, Jason Gunthorpe wrote:
> @@ -184,12 +197,28 @@ static int zynq_fpga_ops_write_init(struct fpga_manager *mgr, u32 flags,
>
> priv = mgr->priv;
>
> + /* The hardware can only DMA multiples of 4 bytes, and we need at
> + * least the sync word and something else to do anything.
> + */
> + if (count <= 4 || (count % 4) != 0) {
> + dev_err(priv->dev,
> + "Invalid bitstream size, must be multiples of 4 bytes\n");
> + return -EINVAL;
> + }
> +
> err = clk_enable(priv->clk);
> if (err)
> return err;
>
> /* don't globally reset PL if we're doing partial reconfig */
> if (!(flags & FPGA_MGR_PARTIAL_RECONFIG)) {
> + if (!zynq_fpga_has_sync(buf, count)) {
> + dev_err(priv->dev,
> + "Invalid bitstream, could not find a sync word. Bitstream must be a byte swaped .bin file\n");
Nitpick: byte swaped is a misspelling... and I'm not sure I like the second half of this message.
Maybe something like "Bitstream must be lsb first" (if that is what is meant).
> + err = -EINVAL;
> + goto out_err;
> + }
> +
> /* assert AXI interface resets */
> regmap_write(priv->slcr, SLCR_FPGA_RST_CTRL_OFFSET,
> FPGA_RST_ALL_MASK);
>
Thanks,
Joshua
next prev parent reply other threads:[~2016-11-10 0:04 UTC|newest]
Thread overview: 43+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-11-09 22:58 [PATCH fpga 0/9] Zynq FPGA Manager Improvements Jason Gunthorpe
2016-11-09 22:58 ` [PATCH fpga 1/9] fpga zynq: Add missing \n to messages Jason Gunthorpe
2016-11-15 11:05 ` Matthias Brugger
2016-11-15 18:08 ` Jason Gunthorpe
2016-11-16 18:39 ` Moritz Fischer
2016-11-16 20:17 ` Jason Gunthorpe
2016-11-16 22:28 ` atull
2016-11-16 22:43 ` Moritz Fischer
2016-11-16 23:55 ` Jason Gunthorpe
2016-11-17 11:32 ` Matthias Brugger
2016-11-09 22:58 ` [PATCH fpga 2/9] fpga zynq: Check the bitstream for validity Jason Gunthorpe
2016-11-10 0:04 ` Joshua Clayton [this message]
2016-11-10 4:58 ` Jason Gunthorpe
2016-11-09 22:58 ` [PATCH fpga 3/9] fpga zynq: Fix incorrect ISR state on bootup Jason Gunthorpe
2016-11-11 0:44 ` Moritz Fischer
2016-11-11 0:53 ` Jason Gunthorpe
2016-11-09 22:58 ` [PATCH fpga 4/9] fpga zynq: Check for errors after completing DMA Jason Gunthorpe
2016-11-17 6:10 ` Moritz Fischer
2016-11-17 18:28 ` Jason Gunthorpe
2016-11-09 22:58 ` [PATCH fpga 5/9] fpga zynq: Remove priv->dev Jason Gunthorpe
2016-11-14 15:13 ` atull
2016-11-14 17:20 ` Moritz Fischer
2016-11-14 23:04 ` Jason Gunthorpe
2016-11-17 18:00 ` Moritz Fischer
2016-11-09 22:58 ` [PATCH fpga 6/9] fpga: Add scatterlist based write ops to the driver ops Jason Gunthorpe
2016-11-09 22:58 ` [PATCH fpga 7/9] fpga zynq: Use the scatterlist interface Jason Gunthorpe
2016-11-09 22:58 ` [PATCH fpga 8/9] fpga socfpga: " Jason Gunthorpe
2016-11-13 23:19 ` atull
2016-11-14 0:18 ` Jason Gunthorpe
2016-11-14 4:02 ` atull
2016-11-15 4:35 ` Jason Gunthorpe
2016-11-15 15:47 ` atull
2016-11-16 5:20 ` Jason Gunthorpe
2016-11-16 15:45 ` atull
2016-11-16 20:23 ` Jason Gunthorpe
2016-11-17 19:54 ` atull
2016-11-17 20:35 ` atull
2016-11-09 22:58 ` [PATCH fpga 9/9] fpga: Remove support for non-sg drivers Jason Gunthorpe
2016-11-10 15:22 ` Joshua Clayton
2016-11-10 16:33 ` Jason Gunthorpe
2016-11-10 22:07 ` Joshua Clayton
2016-11-13 20:44 ` atull
2016-11-13 22:13 ` Jason Gunthorpe
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