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Received: from BN5PR12MB9511.namprd12.prod.outlook.com (2603:10b6:408:2a9::14) by MW4PR12MB7168.namprd12.prod.outlook.com (2603:10b6:303:22d::10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9499.7; Tue, 13 Jan 2026 05:09:42 +0000 Received: from BN5PR12MB9511.namprd12.prod.outlook.com ([fe80::4d8d:5f91:6c3c:dc8c]) by BN5PR12MB9511.namprd12.prod.outlook.com ([fe80::4d8d:5f91:6c3c:dc8c%4]) with mapi id 15.20.9499.005; Tue, 13 Jan 2026 05:09:38 +0000 Message-ID: <17aa80a5-08ce-4aee-b7bb-7310b97ea9db@nvidia.com> Date: Tue, 13 Jan 2026 10:39:30 +0530 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH V7 3/4] dt-bindings: iommu: Add NVIDIA Tegra CMDQV support To: Jon Hunter , will@kernel.org, robin.murphy@arm.com, joro@8bytes.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, nicolinc@nvidia.com Cc: thierry.reding@gmail.com, vdumpa@nvidia.com, jgg@ziepe.ca, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org References: <20251215064819.3345361-1-amhetre@nvidia.com> <20251215064819.3345361-4-amhetre@nvidia.com> <38364cfe-8fc9-4ed7-9034-4e67584ee965@nvidia.com> <9c13e838-6fe5-433c-b361-7d19d1b2ce1e@nvidia.com> <4488ab67-8d41-4095-a1b3-a109e6392890@nvidia.com> Content-Language: en-US From: Ashish Mhetre In-Reply-To: <4488ab67-8d41-4095-a1b3-a109e6392890@nvidia.com> Content-Type: text/plain; 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It assists in >>>>> virtualizing the command queue for the SMMU. >>>>> >>>>> Add a new device tree binding document for nvidia,tegra264-cmdqv. >>>>> >>>>> Also update the arm,smmu-v3 binding to include an optional >>>>> nvidia,cmdqv >>>>> property. This property is a phandle to the CMDQV device node, >>>>> allowing >>>>> the SMMU driver to associate with its corresponding CMDQV instance. >>>>> Restrict this property usage to Nvidia Tegra264 only. >>>>> >>>>> Reviewed-by: Rob Herring (Arm) >>>>> Signed-off-by: Ashish Mhetre >>>>> --- >>>>>   .../bindings/iommu/arm,smmu-v3.yaml           | 30 ++++++++++++- >>>>>   .../bindings/iommu/nvidia,tegra264-cmdqv.yaml | 42 >>>>> +++++++++++++++ ++++ >>>>>   2 files changed, 70 insertions(+), 2 deletions(-) >>>>>   create mode 100644 >>>>> Documentation/devicetree/bindings/iommu/nvidia,tegra264-cmdqv.yaml >>>>> >>>>> diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml >>>>> b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml >>>>> index 75fcf4cb52d9..1c03482e4c61 100644 >>>>> --- a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml >>>>> +++ b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml >>>>> @@ -20,7 +20,12 @@ properties: >>>>>     $nodename: >>>>>       pattern: "^iommu@[0-9a-f]*" >>>>>     compatible: >>>>> -    const: arm,smmu-v3 >>>>> +    oneOf: >>>>> +      - const: arm,smmu-v3 >>>>> +      - items: >>>>> +          - enum: >>>>> +              - nvidia,tegra264-smmu >>>>> +          - const: arm,smmu-v3 >>>>>       reg: >>>>>       maxItems: 1 >>>>> @@ -58,6 +63,15 @@ properties: >>>>>       msi-parent: true >>>>>   +  nvidia,cmdqv: >>>>> +    description: | >>>>> +      A phandle to its pairing CMDQV extension for an implementation >>>>> on NVIDIA >>>>> +      Tegra SoC. >>>>> + >>>>> +      If this property is absent, CMDQ-Virtualization won't be used >>>>> and SMMU >>>>> +      will only use its own CMDQ. >>>>> +    $ref: /schemas/types.yaml#/definitions/phandle >>>>> + >>>>>     hisilicon,broken-prefetch-cmd: >>>>>       type: boolean >>>>>       description: Avoid sending CMD_PREFETCH_* commands to the SMMU. >>>>> @@ -69,6 +83,17 @@ properties: >>>>>         register access with page 0 offsets. Set for Cavium ThunderX2 >>>>> silicon that >>>>>         doesn't support SMMU page1 register space. >>>>>   +allOf: >>>>> +  - if: >>>>> +      not: >>>>> +        properties: >>>>> +          compatible: >>>>> +            contains: >>>>> +              const: nvidia,tegra264-smmu >>>>> +    then: >>>>> +      properties: >>>>> +        nvidia,cmdqv: false >>>>> + >>>>>   required: >>>>>     - compatible >>>>>     - reg >>>>> @@ -82,7 +107,7 @@ examples: >>>>>       #include >>>>>         iommu@2b400000 { >>>>> -            compatible = "arm,smmu-v3"; >>>>> +            compatible = "nvidia,tegra264-smmu", "arm,smmu-v3"; >>>>>               reg = <0x2b400000 0x20000>; >>>>>               interrupts = , >>>>>                            , >>>>> @@ -92,4 +117,5 @@ examples: >>>>>               dma-coherent; >>>>>               #iommu-cells = <1>; >>>>>               msi-parent = <&its 0xff0000>; >>>>> +            nvidia,cmdqv = <&cmdqv>; >>>> >>>> So I believe that this is a generic example for arm,smmu-v3, and so I >>>> am not sure we want to be adding all these NVIDIA specific bits here. >>>> What would be more appropriate is to add another example under the >>>> existing example specifically for Tegra264. >>>> >>>> Jon >>>> >>> >>> Yeah, makes sense. However, I checked arm-smmu.yaml (v2) binding docs >>> and we had separate Nvidia specific compatible and property >>> (nvidia,memory-controller) there as well. But we didn't have a separate >>> example for showing this compatible and property. So, I wonder if we >>> even need to update the generic smmuv3 example for cmdqv property or >>> add a new example? >>> Can you all please share your inputs on this? >>> If required, I'll update the patch will the change below: >>> >>> >>> diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml >>> b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml >>> index 1c03482e4c61..6b07ca9928a7 100644 >>> --- a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml >>> +++ b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml >>> @@ -107,7 +107,7 @@ examples: >>>      #include >>> >>>      iommu@2b400000 { >>> -            compatible = "nvidia,tegra264-smmu", "arm,smmu-v3"; >>> +            compatible = "arm,smmu-v3"; >>>              reg = <0x2b400000 0x20000>; >>>              interrupts = , >>>                           , >>> @@ -117,5 +117,26 @@ examples: >>>              dma-coherent; >>>              #iommu-cells = <1>; >>>              msi-parent = <&its 0xff0000>; >>> +    }; >>> + >>> +  - |+ >>> +    /* Example for NVIDIA Tegra264 with CMDQV extension */ >>> +    #include >>> +    #include >>> + >>> +    iommu@5000000 { >>> +            compatible = "nvidia,tegra264-smmu", "arm,smmu-v3"; >>> +            reg = <0x5000000 0x200000>; >>> +            interrupts = , >>> +                         ; >>> +            interrupt-names = "eventq", "gerror"; >>> +            dma-coherent; >>> +            #iommu-cells = <1>; >>>              nvidia,cmdqv = <&cmdqv>; >>>      }; >>> + >>> +    cmdqv: cmdqv@5200000 { >>> +            compatible = "nvidia,tegra264-cmdqv"; >>> +            reg = <0x5200000 0x830000>; >>> +            interrupts = ; >>> +    }; >>> >>> Thanks, >>> Ashish Mhetre >>> >> >> Hi All, >> >> Can you please share your inputs on this? > > I don't have any strong feelings, but we should leave the existing > example as is and then up to you if you want to add another example > for Tegra. The various DTB build checks will catch any errors in our > DTBs and so I don't believe another example is strictly necessary. > > Jon > Thanks Jon. I will remove the example for Nvidia in next version. Thanks, Ashish Mhetre