[PATCH v5 0/7] Add some enhancements for i.MX95 PCIe

[PATCH v5 0/7] Add some enhancements for i.MX95 PCIe

[Richard Zhu]

v5 changes:
- Rebase to v6.15-rc1
- Update the commit message of "PCI: imx6: Skip one dw_pcie_wait_for_link() in"

v4 changes:
- Add another patch to skip one dw_pcie_wait_for_link() in the workaround link
  training refer to Mani' suggestion.
- Rephrase the comments in "PCI: imx6: Toggle the cold reset for i.MX95 PCIe".
- Correct the error return in "PCI: imx6: Add PLL clock lock check for i.MX95 PCIe".
- Collect and add the Reviewd-by tags.

v3 changes:
- Correct the typo error in first patch, and update the commit message of
  #1 and #6 pathes.
- Use a quirk flag to specify the errata workaround contained in post_init.

v2 changes:
- Correct typo error, and update commit message.
- Replace regmap_update_bits() by regmap_set_bits/regmap_clear_bits.
- Use post_init callback of dw_pcie_host_ops.
- Add one more PLL lock check patch.
- Reformat LUT save and restore functions.

[PATCH v5 1/7] PCI: imx6: Start link directly when workaround is not
[PATCH v5 2/7] PCI: imx6: Skip one dw_pcie_wait_for_link() in
[PATCH v5 3/7] PCI: imx6: Toggle the cold reset for i.MX95 PCIe
[PATCH v5 4/7] PCI: imx6: Workaround i.MX95 PCIe may not exit L23
[PATCH v5 5/7] PCI: imx6: Let i.MX95 PCIe compliance with 8GT/s
[PATCH v5 6/7] PCI: imx6: Add PLL clock lock check for i.MX95 PCIe
[PATCH v5 7/7] PCI: imx6: Save and restore the LUT setting for i.MX95

drivers/pci/controller/dwc/pci-imx6.c | 212 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++------------------
1 file changed, 179 insertions(+), 33 deletions(-)

[PATCH v5 1/7] PCI: imx6: Start link directly when workaround is not required

[Richard Zhu]

The current link setup procedure is one workaround to detect the device
behind PCIe switches on some i.MX6 platforms.

To describe more accurately, change the flag name from
IMX_PCIE_FLAG_IMX_SPEED_CHANGE to IMX_PCIE_FLAG_SPEED_CHANGE_WORKAROUND.

Start PCIe link directly when this flag is not set on i.MX7 or later
platforms to simple and speed up link training.

Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
 drivers/pci/controller/dwc/pci-imx6.c | 34 +++++++++++----------------
 1 file changed, 14 insertions(+), 20 deletions(-)

diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
index 5f267dd261b5..a4c0714c6468 100644
--- a/drivers/pci/controller/dwc/pci-imx6.c
+++ b/drivers/pci/controller/dwc/pci-imx6.c
@@ -91,7 +91,7 @@ enum imx_pcie_variants {
 };
 
 #define IMX_PCIE_FLAG_IMX_PHY			BIT(0)
-#define IMX_PCIE_FLAG_IMX_SPEED_CHANGE		BIT(1)
+#define IMX_PCIE_FLAG_SPEED_CHANGE_WORKAROUND	BIT(1)
 #define IMX_PCIE_FLAG_SUPPORTS_SUSPEND		BIT(2)
 #define IMX_PCIE_FLAG_HAS_PHYDRV		BIT(3)
 #define IMX_PCIE_FLAG_HAS_APP_RESET		BIT(4)
@@ -860,6 +860,12 @@ static int imx_pcie_start_link(struct dw_pcie *pci)
 	u32 tmp;
 	int ret;
 
+	if (!(imx_pcie->drvdata->flags &
+	    IMX_PCIE_FLAG_SPEED_CHANGE_WORKAROUND)) {
+		imx_pcie_ltssm_enable(dev);
+		return 0;
+	}
+
 	/*
 	 * Force Gen1 operation when starting the link.  In case the link is
 	 * started in Gen2 mode, there is a possibility the devices on the
@@ -896,22 +902,10 @@ static int imx_pcie_start_link(struct dw_pcie *pci)
 		dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, tmp);
 		dw_pcie_dbi_ro_wr_dis(pci);
 
-		if (imx_pcie->drvdata->flags &
-		    IMX_PCIE_FLAG_IMX_SPEED_CHANGE) {
-
-			/*
-			 * On i.MX7, DIRECT_SPEED_CHANGE behaves differently
-			 * from i.MX6 family when no link speed transition
-			 * occurs and we go Gen1 -> yep, Gen1. The difference
-			 * is that, in such case, it will not be cleared by HW
-			 * which will cause the following code to report false
-			 * failure.
-			 */
-			ret = imx_pcie_wait_for_speed_change(imx_pcie);
-			if (ret) {
-				dev_err(dev, "Failed to bring link up!\n");
-				goto err_reset_phy;
-			}
+		ret = imx_pcie_wait_for_speed_change(imx_pcie);
+		if (ret) {
+			dev_err(dev, "Failed to bring link up!\n");
+			goto err_reset_phy;
 		}
 
 		/* Make sure link training is finished as well! */
@@ -1649,7 +1643,7 @@ static const struct imx_pcie_drvdata drvdata[] = {
 	[IMX6Q] = {
 		.variant = IMX6Q,
 		.flags = IMX_PCIE_FLAG_IMX_PHY |
-			 IMX_PCIE_FLAG_IMX_SPEED_CHANGE |
+			 IMX_PCIE_FLAG_SPEED_CHANGE_WORKAROUND |
 			 IMX_PCIE_FLAG_BROKEN_SUSPEND |
 			 IMX_PCIE_FLAG_SUPPORTS_SUSPEND,
 		.dbi_length = 0x200,
@@ -1665,7 +1659,7 @@ static const struct imx_pcie_drvdata drvdata[] = {
 	[IMX6SX] = {
 		.variant = IMX6SX,
 		.flags = IMX_PCIE_FLAG_IMX_PHY |
-			 IMX_PCIE_FLAG_IMX_SPEED_CHANGE |
+			 IMX_PCIE_FLAG_SPEED_CHANGE_WORKAROUND |
 			 IMX_PCIE_FLAG_SUPPORTS_SUSPEND,
 		.gpr = "fsl,imx6q-iomuxc-gpr",
 		.ltssm_off = IOMUXC_GPR12,
@@ -1680,7 +1674,7 @@ static const struct imx_pcie_drvdata drvdata[] = {
 	[IMX6QP] = {
 		.variant = IMX6QP,
 		.flags = IMX_PCIE_FLAG_IMX_PHY |
-			 IMX_PCIE_FLAG_IMX_SPEED_CHANGE |
+			 IMX_PCIE_FLAG_SPEED_CHANGE_WORKAROUND |
 			 IMX_PCIE_FLAG_SUPPORTS_SUSPEND,
 		.dbi_length = 0x200,
 		.gpr = "fsl,imx6q-iomuxc-gpr",
-- 
2.37.1

[PATCH v5 2/7] PCI: imx6: Skip one dw_pcie_wait_for_link() in workaround link training

[Richard Zhu]

Remove one reduntant dw_pcie_wait_for_link() in link traning workaround
because common framework already do that.

Suggested-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
---
 drivers/pci/controller/dwc/pci-imx6.c | 15 ++++-----------
 1 file changed, 4 insertions(+), 11 deletions(-)

diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
index a4c0714c6468..c5871c3d4194 100644
--- a/drivers/pci/controller/dwc/pci-imx6.c
+++ b/drivers/pci/controller/dwc/pci-imx6.c
@@ -881,11 +881,11 @@ static int imx_pcie_start_link(struct dw_pcie *pci)
 	/* Start LTSSM. */
 	imx_pcie_ltssm_enable(dev);
 
-	ret = dw_pcie_wait_for_link(pci);
-	if (ret)
-		goto err_reset_phy;
-
 	if (pci->max_link_speed > 1) {
+		ret = dw_pcie_wait_for_link(pci);
+		if (ret)
+			goto err_reset_phy;
+
 		/* Allow faster modes after the link is up */
 		dw_pcie_dbi_ro_wr_en(pci);
 		tmp = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP);
@@ -907,17 +907,10 @@ static int imx_pcie_start_link(struct dw_pcie *pci)
 			dev_err(dev, "Failed to bring link up!\n");
 			goto err_reset_phy;
 		}
-
-		/* Make sure link training is finished as well! */
-		ret = dw_pcie_wait_for_link(pci);
-		if (ret)
-			goto err_reset_phy;
 	} else {
 		dev_info(dev, "Link: Only Gen1 is enabled\n");
 	}
 
-	tmp = dw_pcie_readw_dbi(pci, offset + PCI_EXP_LNKSTA);
-	dev_info(dev, "Link up, Gen%i\n", tmp & PCI_EXP_LNKSTA_CLS);
 	return 0;
 
 err_reset_phy:
-- 
2.37.1

[PATCH v5 3/7] PCI: imx6: Toggle the cold reset for i.MX95 PCIe

[Richard Zhu]

Add the cold reset toggle for i.MX95 PCIe to align PHY's power up sequency.

Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
---
 drivers/pci/controller/dwc/pci-imx6.c | 42 +++++++++++++++++++++++++++
 1 file changed, 42 insertions(+)

diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
index c5871c3d4194..7c60b712480a 100644
--- a/drivers/pci/controller/dwc/pci-imx6.c
+++ b/drivers/pci/controller/dwc/pci-imx6.c
@@ -71,6 +71,9 @@
 #define IMX95_SID_MASK				GENMASK(5, 0)
 #define IMX95_MAX_LUT				32
 
+#define IMX95_PCIE_RST_CTRL			0x3010
+#define IMX95_PCIE_COLD_RST			BIT(0)
+
 #define to_imx_pcie(x)	dev_get_drvdata((x)->dev)
 
 enum imx_pcie_variants {
@@ -773,6 +776,43 @@ static int imx7d_pcie_core_reset(struct imx_pcie *imx_pcie, bool assert)
 	return 0;
 }
 
+static int imx95_pcie_core_reset(struct imx_pcie *imx_pcie, bool assert)
+{
+	u32 val;
+
+	if (assert) {
+		/*
+		 * From i.MX95 PCIe PHY perspective, the COLD reset toggle
+		 * should be complete after power-up by the following sequence.
+		 *                 > 10us(at power-up)
+		 *                 > 10ns(warm reset)
+		 *               |<------------>|
+		 *                ______________
+		 * phy_reset ____/              \________________
+		 *                                   ____________
+		 * ref_clk_en_______________________/
+		 * Toggle COLD reset aligned with this sequence for i.MX95 PCIe.
+		 */
+		regmap_set_bits(imx_pcie->iomuxc_gpr, IMX95_PCIE_RST_CTRL,
+				IMX95_PCIE_COLD_RST);
+		/*
+		 * Make sure the write to IMX95_PCIE_RST_CTRL is flushed to the
+		 * hardware by doing a read. Otherwise, there is no guarantee
+		 * that the write has reached the hardware before udelay().
+		 */
+		regmap_read_bypassed(imx_pcie->iomuxc_gpr, IMX95_PCIE_RST_CTRL,
+				     &val);
+		udelay(15);
+		regmap_clear_bits(imx_pcie->iomuxc_gpr, IMX95_PCIE_RST_CTRL,
+				  IMX95_PCIE_COLD_RST);
+		regmap_read_bypassed(imx_pcie->iomuxc_gpr, IMX95_PCIE_RST_CTRL,
+				     &val);
+		udelay(10);
+	}
+
+	return 0;
+}
+
 static void imx_pcie_assert_core_reset(struct imx_pcie *imx_pcie)
 {
 	reset_control_assert(imx_pcie->pciephy_reset);
@@ -1739,6 +1779,7 @@ static const struct imx_pcie_drvdata drvdata[] = {
 		.ltssm_mask = IMX95_PCIE_LTSSM_EN,
 		.mode_off[0]  = IMX95_PE0_GEN_CTRL_1,
 		.mode_mask[0] = IMX95_PCIE_DEVICE_TYPE,
+		.core_reset = imx95_pcie_core_reset,
 		.init_phy = imx95_pcie_init_phy,
 	},
 	[IMX8MQ_EP] = {
@@ -1792,6 +1833,7 @@ static const struct imx_pcie_drvdata drvdata[] = {
 		.mode_off[0]  = IMX95_PE0_GEN_CTRL_1,
 		.mode_mask[0] = IMX95_PCIE_DEVICE_TYPE,
 		.init_phy = imx95_pcie_init_phy,
+		.core_reset = imx95_pcie_core_reset,
 		.epc_features = &imx95_pcie_epc_features,
 		.mode = DW_PCIE_EP_TYPE,
 	},
-- 
2.37.1

[PATCH v5 4/7] PCI: imx6: Workaround i.MX95 PCIe may not exit L23 ready

[Richard Zhu]

ERR051624: The Controller Without Vaux Cannot Exit L23 Ready Through Beacon
or PERST# De-assertion

When the auxiliary power is not available, the controller cannot exit from
L23 Ready with beacon or PERST# de-assertion when main power is not
removed.

Workaround: Set SS_RW_REG_1[SYS_AUX_PWR_DET] to 1.

Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
---
 drivers/pci/controller/dwc/pci-imx6.c | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
index 7c60b712480a..016b86add959 100644
--- a/drivers/pci/controller/dwc/pci-imx6.c
+++ b/drivers/pci/controller/dwc/pci-imx6.c
@@ -48,6 +48,8 @@
 #define IMX95_PCIE_SS_RW_REG_0			0xf0
 #define IMX95_PCIE_REF_CLKEN			BIT(23)
 #define IMX95_PCIE_PHY_CR_PARA_SEL		BIT(9)
+#define IMX95_PCIE_SS_RW_REG_1			0xf4
+#define IMX95_PCIE_SYS_AUX_PWR_DET		BIT(31)
 
 #define IMX95_PE0_GEN_CTRL_1			0x1050
 #define IMX95_PCIE_DEVICE_TYPE			GENMASK(3, 0)
@@ -227,6 +229,19 @@ static unsigned int imx_pcie_grp_offset(const struct imx_pcie *imx_pcie)
 
 static int imx95_pcie_init_phy(struct imx_pcie *imx_pcie)
 {
+	/*
+	 * ERR051624: The Controller Without Vaux Cannot Exit L23 Ready
+	 * Through Beacon or PERST# De-assertion
+	 *
+	 * When the auxiliary power is not available, the controller
+	 * cannot exit from L23 Ready with beacon or PERST# de-assertion
+	 * when main power is not removed.
+	 *
+	 * Workaround: Set SS_RW_REG_1[SYS_AUX_PWR_DET] to 1.
+	 */
+	regmap_set_bits(imx_pcie->iomuxc_gpr, IMX95_PCIE_SS_RW_REG_1,
+			IMX95_PCIE_SYS_AUX_PWR_DET);
+
 	regmap_update_bits(imx_pcie->iomuxc_gpr,
 			IMX95_PCIE_SS_RW_REG_0,
 			IMX95_PCIE_PHY_CR_PARA_SEL,
-- 
2.37.1

[PATCH v5 5/7] PCI: imx6: Let i.MX95 PCIe compliance with 8GT/s Receiver Impedance ECN

[Richard Zhu]

ERR051586: Compliance with 8GT/s Receiver Impedance ECN.

The default value of GEN3_RELATED_OFF[GEN3_ZRXDC_NONCOMPL] is 1 which
makes receiver non-compliant with the ZRX-DC parameter for 2.5 GT/s when
operating at 8 GT/s or higher. It causes unnecessary timeout in L1.

Workaround: Program GEN3_RELATED_OFF[GEN3_ZRXDC_NONCOMPL] to 0.

Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
 drivers/pci/controller/dwc/pci-imx6.c | 31 +++++++++++++++++++++++++++
 1 file changed, 31 insertions(+)

diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
index 016b86add959..7dcc9d88740d 100644
--- a/drivers/pci/controller/dwc/pci-imx6.c
+++ b/drivers/pci/controller/dwc/pci-imx6.c
@@ -110,6 +110,7 @@ enum imx_pcie_variants {
  */
 #define IMX_PCIE_FLAG_BROKEN_SUSPEND		BIT(9)
 #define IMX_PCIE_FLAG_HAS_LUT			BIT(10)
+#define IMX_PCIE_FLAG_8GT_ECN_ERR051586		BIT(11)
 
 #define imx_check_flag(pci, val)	(pci->drvdata->flags & val)
 
@@ -1256,6 +1257,32 @@ static void imx_pcie_host_exit(struct dw_pcie_rp *pp)
 		regulator_disable(imx_pcie->vpcie);
 }
 
+static void imx_pcie_host_post_init(struct dw_pcie_rp *pp)
+{
+	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
+	struct imx_pcie *imx_pcie = to_imx_pcie(pci);
+	u32 val;
+
+	if (imx_pcie->drvdata->flags & IMX_PCIE_FLAG_8GT_ECN_ERR051586) {
+		/*
+		 * ERR051586: Compliance with 8GT/s Receiver Impedance ECN
+		 *
+		 * The default value of GEN3_RELATED_OFF[GEN3_ZRXDC_NONCOMPL]
+		 * is 1 which makes receiver non-compliant with the ZRX-DC
+		 * parameter for 2.5 GT/s when operating at 8 GT/s or higher.
+		 * It causes unnecessary timeout in L1.
+		 *
+		 * Workaround: Program GEN3_RELATED_OFF[GEN3_ZRXDC_NONCOMPL]
+		 * to 0.
+		 */
+		dw_pcie_dbi_ro_wr_en(pci);
+		val = dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF);
+		val &= ~GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL;
+		dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, val);
+		dw_pcie_dbi_ro_wr_dis(pci);
+	}
+}
+
 /*
  * In old DWC implementations, PCIE_ATU_INHIBIT_PAYLOAD in iATU Ctrl2
  * register is reserved, so the generic DWC implementation of sending the
@@ -1281,6 +1308,7 @@ static const struct dw_pcie_host_ops imx_pcie_host_ops = {
 static const struct dw_pcie_host_ops imx_pcie_host_dw_pme_ops = {
 	.init = imx_pcie_host_init,
 	.deinit = imx_pcie_host_exit,
+	.post_init = imx_pcie_host_post_init,
 };
 
 static const struct dw_pcie_ops dw_pcie_ops = {
@@ -1392,6 +1420,7 @@ static int imx_add_pcie_ep(struct imx_pcie *imx_pcie,
 		dev_err(dev, "failed to initialize endpoint\n");
 		return ret;
 	}
+	imx_pcie_host_post_init(pp);
 
 	ret = dw_pcie_ep_init_registers(ep);
 	if (ret) {
@@ -1789,6 +1818,7 @@ static const struct imx_pcie_drvdata drvdata[] = {
 		.variant = IMX95,
 		.flags = IMX_PCIE_FLAG_HAS_SERDES |
 			 IMX_PCIE_FLAG_HAS_LUT |
+			 IMX_PCIE_FLAG_8GT_ECN_ERR051586 |
 			 IMX_PCIE_FLAG_SUPPORTS_SUSPEND,
 		.ltssm_off = IMX95_PE0_GEN_CTRL_3,
 		.ltssm_mask = IMX95_PCIE_LTSSM_EN,
@@ -1842,6 +1872,7 @@ static const struct imx_pcie_drvdata drvdata[] = {
 	[IMX95_EP] = {
 		.variant = IMX95_EP,
 		.flags = IMX_PCIE_FLAG_HAS_SERDES |
+			 IMX_PCIE_FLAG_8GT_ECN_ERR051586 |
 			 IMX_PCIE_FLAG_SUPPORT_64BIT,
 		.ltssm_off = IMX95_PE0_GEN_CTRL_3,
 		.ltssm_mask = IMX95_PCIE_LTSSM_EN,
-- 
2.37.1

[PATCH v5 6/7] PCI: imx6: Add PLL clock lock check for i.MX95 PCIe

[Richard Zhu]

Add PLL clock lock check for i.MX95 PCIe.

Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
---
 drivers/pci/controller/dwc/pci-imx6.c | 28 +++++++++++++++++++++++++--
 1 file changed, 26 insertions(+), 2 deletions(-)

diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
index 7dcc9d88740d..c1d128ec255d 100644
--- a/drivers/pci/controller/dwc/pci-imx6.c
+++ b/drivers/pci/controller/dwc/pci-imx6.c
@@ -45,6 +45,9 @@
 #define IMX95_PCIE_PHY_GEN_CTRL			0x0
 #define IMX95_PCIE_REF_USE_PAD			BIT(17)
 
+#define IMX95_PCIE_PHY_MPLLA_CTRL		0x10
+#define IMX95_PCIE_PHY_MPLL_STATE		BIT(30)
+
 #define IMX95_PCIE_SS_RW_REG_0			0xf0
 #define IMX95_PCIE_REF_CLKEN			BIT(23)
 #define IMX95_PCIE_PHY_CR_PARA_SEL		BIT(9)
@@ -479,6 +482,23 @@ static void imx7d_pcie_wait_for_phy_pll_lock(struct imx_pcie *imx_pcie)
 		dev_err(dev, "PCIe PLL lock timeout\n");
 }
 
+static int imx95_pcie_wait_for_phy_pll_lock(struct imx_pcie *imx_pcie)
+{
+	u32 val;
+	struct device *dev = imx_pcie->pci->dev;
+
+	if (regmap_read_poll_timeout(imx_pcie->iomuxc_gpr,
+				     IMX95_PCIE_PHY_MPLLA_CTRL, val,
+				     val & IMX95_PCIE_PHY_MPLL_STATE,
+				     PHY_PLL_LOCK_WAIT_USLEEP_MAX,
+				     PHY_PLL_LOCK_WAIT_TIMEOUT)) {
+		dev_err(dev, "PCIe PLL lock timeout\n");
+		return -ETIMEDOUT;
+	}
+
+	return 0;
+}
+
 static int imx_setup_phy_mpll(struct imx_pcie *imx_pcie)
 {
 	unsigned long phy_rate = 0;
@@ -824,6 +844,8 @@ static int imx95_pcie_core_reset(struct imx_pcie *imx_pcie, bool assert)
 		regmap_read_bypassed(imx_pcie->iomuxc_gpr, IMX95_PCIE_RST_CTRL,
 				     &val);
 		udelay(10);
+	} else {
+		return imx95_pcie_wait_for_phy_pll_lock(imx_pcie);
 	}
 
 	return 0;
@@ -843,11 +865,13 @@ static void imx_pcie_assert_core_reset(struct imx_pcie *imx_pcie)
 
 static int imx_pcie_deassert_core_reset(struct imx_pcie *imx_pcie)
 {
+	int ret = 0;
+
 	reset_control_deassert(imx_pcie->pciephy_reset);
 	reset_control_deassert(imx_pcie->apps_reset);
 
 	if (imx_pcie->drvdata->core_reset)
-		imx_pcie->drvdata->core_reset(imx_pcie, false);
+		ret = imx_pcie->drvdata->core_reset(imx_pcie, false);
 
 	/* Some boards don't have PCIe reset GPIO. */
 	if (imx_pcie->reset_gpiod) {
@@ -857,7 +881,7 @@ static int imx_pcie_deassert_core_reset(struct imx_pcie *imx_pcie)
 		msleep(100);
 	}
 
-	return 0;
+	return ret;
 }
 
 static int imx_pcie_wait_for_speed_change(struct imx_pcie *imx_pcie)
-- 
2.37.1

[PATCH v5 7/7] PCI: imx6: Save and restore the LUT setting for i.MX95 PCIe

[Richard Zhu]

The look up table(LUT) setting would be lost during PCIe suspend on i.MX95.

To ensure proper functionality after resume, save and restore the LUT
setting in suspend and resume operations.

Fixes: 9d6b1bd6b3c8 ("PCI: imx6: Add i.MX8MQ, i.MX8Q and i.MX95 PM support")
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
 drivers/pci/controller/dwc/pci-imx6.c | 47 +++++++++++++++++++++++++++
 1 file changed, 47 insertions(+)

diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
index c1d128ec255d..523bd3e11ff4 100644
--- a/drivers/pci/controller/dwc/pci-imx6.c
+++ b/drivers/pci/controller/dwc/pci-imx6.c
@@ -138,6 +138,11 @@ struct imx_pcie_drvdata {
 	const struct dw_pcie_host_ops *ops;
 };
 
+struct imx_lut_data {
+	u32 data1;
+	u32 data2;
+};
+
 struct imx_pcie {
 	struct dw_pcie		*pci;
 	struct gpio_desc	*reset_gpiod;
@@ -157,6 +162,8 @@ struct imx_pcie {
 	struct regulator	*vph;
 	void __iomem		*phy_base;
 
+	/* LUT data for pcie */
+	struct imx_lut_data	luts[IMX95_MAX_LUT];
 	/* power domain for pcie */
 	struct device		*pd_pcie;
 	/* power domain for pcie phy */
@@ -1481,6 +1488,42 @@ static void imx_pcie_msi_save_restore(struct imx_pcie *imx_pcie, bool save)
 	}
 }
 
+static void imx_pcie_lut_save(struct imx_pcie *imx_pcie)
+{
+	u32 data1, data2;
+	int i;
+
+	for (i = 0; i < IMX95_MAX_LUT; i++) {
+		regmap_write(imx_pcie->iomuxc_gpr, IMX95_PE0_LUT_ACSCTRL,
+			     IMX95_PEO_LUT_RWA | i);
+		regmap_read(imx_pcie->iomuxc_gpr, IMX95_PE0_LUT_DATA1, &data1);
+		regmap_read(imx_pcie->iomuxc_gpr, IMX95_PE0_LUT_DATA2, &data2);
+		if (data1 & IMX95_PE0_LUT_VLD) {
+			imx_pcie->luts[i].data1 = data1;
+			imx_pcie->luts[i].data2 = data2;
+		} else {
+			imx_pcie->luts[i].data1 = 0;
+			imx_pcie->luts[i].data2 = 0;
+		}
+	}
+}
+
+static void imx_pcie_lut_restore(struct imx_pcie *imx_pcie)
+{
+	int i;
+
+	for (i = 0; i < IMX95_MAX_LUT; i++) {
+		if ((imx_pcie->luts[i].data1 & IMX95_PE0_LUT_VLD) == 0)
+			continue;
+
+		regmap_write(imx_pcie->iomuxc_gpr, IMX95_PE0_LUT_DATA1,
+			     imx_pcie->luts[i].data1);
+		regmap_write(imx_pcie->iomuxc_gpr, IMX95_PE0_LUT_DATA2,
+			     imx_pcie->luts[i].data2);
+		regmap_write(imx_pcie->iomuxc_gpr, IMX95_PE0_LUT_ACSCTRL, i);
+	}
+}
+
 static int imx_pcie_suspend_noirq(struct device *dev)
 {
 	struct imx_pcie *imx_pcie = dev_get_drvdata(dev);
@@ -1489,6 +1532,8 @@ static int imx_pcie_suspend_noirq(struct device *dev)
 		return 0;
 
 	imx_pcie_msi_save_restore(imx_pcie, true);
+	if (imx_check_flag(imx_pcie, IMX_PCIE_FLAG_HAS_LUT))
+		imx_pcie_lut_save(imx_pcie);
 	if (imx_check_flag(imx_pcie, IMX_PCIE_FLAG_BROKEN_SUSPEND)) {
 		/*
 		 * The minimum for a workaround would be to set PERST# and to
@@ -1533,6 +1578,8 @@ static int imx_pcie_resume_noirq(struct device *dev)
 		if (ret)
 			return ret;
 	}
+	if (imx_check_flag(imx_pcie, IMX_PCIE_FLAG_HAS_LUT))
+		imx_pcie_lut_restore(imx_pcie);
 	imx_pcie_msi_save_restore(imx_pcie, false);
 
 	return 0;
-- 
2.37.1

Re: [PATCH v5 3/7] PCI: imx6: Toggle the cold reset for i.MX95 PCIe

[Alexander Stein]

Hi,

Am Dienstag, 8. April 2025, 04:59:26 CEST schrieb Richard Zhu:
> Add the cold reset toggle for i.MX95 PCIe to align PHY's power up sequency.
> 
> Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
> Reviewed-by: Frank Li <Frank.Li@nxp.com>
> ---
>  drivers/pci/controller/dwc/pci-imx6.c | 42 +++++++++++++++++++++++++++
>  1 file changed, 42 insertions(+)
> 
> diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
> index c5871c3d4194..7c60b712480a 100644
> --- a/drivers/pci/controller/dwc/pci-imx6.c
> +++ b/drivers/pci/controller/dwc/pci-imx6.c
> @@ -71,6 +71,9 @@
>  #define IMX95_SID_MASK				GENMASK(5, 0)
>  #define IMX95_MAX_LUT				32
>  
> +#define IMX95_PCIE_RST_CTRL			0x3010
> +#define IMX95_PCIE_COLD_RST			BIT(0)
> +
>  #define to_imx_pcie(x)	dev_get_drvdata((x)->dev)
>  
>  enum imx_pcie_variants {
> @@ -773,6 +776,43 @@ static int imx7d_pcie_core_reset(struct imx_pcie *imx_pcie, bool assert)
>  	return 0;
>  }
>  
> +static int imx95_pcie_core_reset(struct imx_pcie *imx_pcie, bool assert)
> +{
> +	u32 val;
> +
> +	if (assert) {
> +		/*
> +		 * From i.MX95 PCIe PHY perspective, the COLD reset toggle
> +		 * should be complete after power-up by the following sequence.
> +		 *                 > 10us(at power-up)
> +		 *                 > 10ns(warm reset)
> +		 *               |<------------>|
> +		 *                ______________
> +		 * phy_reset ____/              \________________
> +		 *                                   ____________
> +		 * ref_clk_en_______________________/
> +		 * Toggle COLD reset aligned with this sequence for i.MX95 PCIe.
> +		 */
> +		regmap_set_bits(imx_pcie->iomuxc_gpr, IMX95_PCIE_RST_CTRL,
> +				IMX95_PCIE_COLD_RST);
> +		/*
> +		 * Make sure the write to IMX95_PCIE_RST_CTRL is flushed to the
> +		 * hardware by doing a read. Otherwise, there is no guarantee
> +		 * that the write has reached the hardware before udelay().
> +		 */
> +		regmap_read_bypassed(imx_pcie->iomuxc_gpr, IMX95_PCIE_RST_CTRL,
> +				     &val);
> +		udelay(15);
> +		regmap_clear_bits(imx_pcie->iomuxc_gpr, IMX95_PCIE_RST_CTRL,
> +				  IMX95_PCIE_COLD_RST);
> +		regmap_read_bypassed(imx_pcie->iomuxc_gpr, IMX95_PCIE_RST_CTRL,
> +				     &val);
> +		udelay(10);
> +	}
> +
> +	return 0;
> +}
> +
>  static void imx_pcie_assert_core_reset(struct imx_pcie *imx_pcie)
>  {
>  	reset_control_assert(imx_pcie->pciephy_reset);
> @@ -1739,6 +1779,7 @@ static const struct imx_pcie_drvdata drvdata[] = {
>  		.ltssm_mask = IMX95_PCIE_LTSSM_EN,
>  		.mode_off[0]  = IMX95_PE0_GEN_CTRL_1,
>  		.mode_mask[0] = IMX95_PCIE_DEVICE_TYPE,
> +		.core_reset = imx95_pcie_core_reset,
>  		.init_phy = imx95_pcie_init_phy,
>  	},
>  	[IMX8MQ_EP] = {
> @@ -1792,6 +1833,7 @@ static const struct imx_pcie_drvdata drvdata[] = {
>  		.mode_off[0]  = IMX95_PE0_GEN_CTRL_1,
>  		.mode_mask[0] = IMX95_PCIE_DEVICE_TYPE,
>  		.init_phy = imx95_pcie_init_phy,
> +		.core_reset = imx95_pcie_core_reset,
>  		.epc_features = &imx95_pcie_epc_features,
>  		.mode = DW_PCIE_EP_TYPE,
>  	},
> 

This change introduces an invalid memory access on my platform. There is not
even a PCIe device attached to it.

> imx6q-pcie 4c380000.pcie: host bridge /soc/pcie@4c380000 ranges:
> imx6q-pcie 4c300000.pcie: host bridge /soc/pcie@4c300000 ranges:
> imx6q-pcie 4c380000.pcie:       IO 0x088ff00000..0x088fffffff -> 0x0000000000
> imx6q-pcie 4c300000.pcie:       IO 0x006ff00000..0x006fffffff -> 0x0000000000
> imx6q-pcie 4c380000.pcie:      MEM 0x0a10000000..0x0a1fffffff -> 0x0010000000
> imx6q-pcie 4c300000.pcie:      MEM 0x0910000000..0x091fffffff -> 0x0010000000
> imx6q-pcie 4c380000.pcie: config reg[1] 0x880100000 == cpu 0x880100000
> ; no fixup was ever needed for this devicetree
> imx6q-pcie 4c300000.pcie: config reg[1] 0x60100000 == cpu 0x60100000
> ; no fixup was ever needed for this devicetree
> Unable to handle kernel paging request at virtual address ffff800081dc5010
> Unable to handle kernel paging request at virtual address ffff8000821bd010
> Mem abort info:
> 
> Mem abort info:
>   ESR = 0x0000000096000007
>   ESR = 0x0000000096000007
>   EC = 0x25: DABT (current EL), IL = 32 bits
>   EC = 0x25: DABT (current EL), IL = 32 bits
> 
> fsl_enetc_mdio 0003:01:00.0: enabling device (0000 -> 0002)
> 
>   SET = 0, FnV = 0
>   SET = 0, FnV = 0
>   EA = 0, S1PTW = 0
>   EA = 0, S1PTW = 0
>   FSC = 0x07: level 3 translation fault
>   FSC = 0x07: level 3 translation fault
> 
> Data abort info:
> 
> Data abort info:
>   ISV = 0, ISS = 0x00000007, ISS2 = 0x00000000
>   ISV = 0, ISS = 0x00000007, ISS2 = 0x00000000
>   CM = 0, WnR = 0, TnD = 0, TagAccess = 0
>   CM = 0, WnR = 0, TnD = 0, TagAccess = 0
>   GCS = 0, Overlay = 0, DirtyBit = 0, Xs = 0
>   GCS = 0, Overlay = 0, DirtyBit = 0, Xs = 0
> 
> swapper pgtable: 4k pages, 48-bit VAs, pgdp=0000000091a47000
> swapper pgtable: 4k pages, 48-bit VAs, pgdp=0000000091a47000
> [ffff800081dc5010] pgd=1000000092002003
> [ffff8000821bd010] pgd=1000000092002003
> , p4d=1000000092002003
> , p4d=1000000092002003
> , pud=1000000092003003
> , pud=1000000092003003
> , pmd=1000000092008003
> , pmd=100000009299f403
> , pte=0000000000000000
> , pte=0000000000000000
> 
> 
> Internal error: Oops: 0000000096000007 [#1]  SMP
> Modules linked in:
> CPU: 0 UID: 0 PID: 63 Comm: kworker/u24:4 Tainted: G                T  
> 6.15.0-rc1-next-20250409+ #3009 PREEMPT 
> f6bd3cc6346487744ae55f6115e728ff2bc7088b Tainted: [T]=RANDSTRUCT
> Hardware name: TQ-Systems i.MX95 TQMa95xxSA on MB-SMARC-2 (DT)
> Workqueue: async async_run_entry_fn
> pstate: 204000c9 (nzCv daIF +PAN -UAO -TCO -DIT -SSBS BTYPE=--)
> pc : regmap_mmio_read32le+0x1c/0x3c
> lr : regmap_mmio_read+0x40/0x68
> sp : ffff80008223b860
> x29: ffff80008223b860 x28: ffff00001000c800 x27: ffff8000818679c0
> x26: ffff000013340410 x25: 0000000000000001 x24: 0000000000000000
> x23: ffff000012f5e400 x22: ffff80008223b934 x21: ffff80008223b934
> x20: ffff000012fc4900 x19: 0000000000003010 x18: 00000000a7aa953f
> x17: 3e2d206666666666 x16: 666631393078302e x15: 2e30303030303030
> x14: 3139307830204d45 x13: 3030303030303031 x12: 30307830203e2d20
> x11: 6666666666666631 x10: 393078302e2e3030 x9 : 4d2020202020203a
> x8 : 656963702e303030 x7 : 205d313236353838 x6 : ffff0000134e0000
> x5 : 0000000000000000 x4 : 0000000000000000 x3 : ffff8000809bf028
> x2 : ffff8000809bfb0c x1 : 0000000000003010 x0 : ffff800081dc5010
> 
> Call trace:
>  regmap_mmio_read32le+0x1c/0x3c (P)
>  regmap_mmio_read+0x40/0x68
>  _regmap_bus_reg_read+0x58/0x9c
>  _regmap_read+0x70/0x1c4
>  _regmap_update_bits+0xe4/0x174
>  regmap_update_bits_base+0x60/0x90
>  imx95_pcie_core_reset+0x78/0xd0
>  imx_pcie_assert_core_reset+0x38/0x50
>  imx_pcie_host_init+0x68/0x4a0
>  dw_pcie_host_init+0x16c/0x500
>  imx_pcie_probe+0x2f4/0x71c
>  platform_probe+0x64/0x100
>  really_probe+0xc8/0x3bc
>  __driver_probe_device+0x84/0x16c
>  driver_probe_device+0x40/0x160
>  __device_attach_driver+0xcc/0x1a0
>  bus_for_each_drv+0x88/0xe4
>  __device_attach_async_helper+0xac/0x108
>  async_run_entry_fn+0x30/0x144
>  process_one_work+0x14c/0x3e0
>  worker_thread+0x2f0/0x3fc
>  kthread+0x128/0x1ec
>  ret_from_fork+0x10/0x20
> 
> Code: aa0003f4 2a0103f3 f9400280 8b334000 (b9400000)
> ---[ end trace 0000000000000000 ]---
> note: kworker/u24:4[63] exited with irqs disabled
> Internal error: Oops: 0000000096000007 [#2]  SMP
> Modules linked in:
> note: kworker/u24:4[63] exited with preempt_count 1
> 
> CPU: 4 UID: 0 PID: 52 Comm: kworker/u24:1 Tainted: G      D         T  
> 6.15.0-rc1-next-20250409+ #3009 PREEMPT 
> f6bd3cc6346487744ae55f6115e728ff2bc7088b Tainted: [D]=DIE, [T]=RANDSTRUCT
> Hardware name: TQ-Systems i.MX95 TQMa95xxSA on MB-SMARC-2 (DT)
> Workqueue: async async_run_entry_fn
> pstate: 204000c9 (nzCv daIF +PAN -UAO -TCO -DIT -SSBS BTYPE=--)
> pc : regmap_mmio_read32le+0x1c/0x3c
> lr : regmap_mmio_read+0x40/0x68
> mmc0: new HS400 Enhanced strobe MMC card at address 0001
> sp : ffff8000821e3860
> mmcblk0: mmc0:0001 DG4016 14.7 GiB
> x29: ffff8000821e3860 x28: ffff00001000c800 x27: ffff8000818679c0
> mmcblk0boot0: mmc0:0001 DG4016 4.00 MiB
> x26: ffff00001333fc10 x25: 0000000000000001 x24: 0000000000000000
> x23: ffff000013895400 x22: ffff8000821e3934 x21: ffff8000821e3934
> x20: ffff0000134672c0
> mmcblk0boot1: mmc0:0001 DG4016 4.00 MiB
> 
>  x19: 0000000000003010 x18: 0000000038868210
> 
> x17: 3038387830207570 x16: 63203d3d20303030 x15: 3030313038387830
> x14: 205d315b67657220
> mmcblk0rpmb: mmc0:0001 DG4016 4.00 MiB, chardev (237:0)
> 
>  x13: 6565727465636976 x12: 6564207369687420
> 
> x11: 726f662064656465 x10: 656e207265766520 x9 : 7420726f66206465
> x8 : 6465656e20726576 x7 : 205d303033353938 x6 : ffff000013371280
> x5 : 0000000000000000 x4 : 0000000000000000 x3 : ffff8000809bf028
> x2 : ffff8000809bfb0c x1 : 0000000000003010 x0 : ffff8000821bd010
> 
> Call trace:
>  regmap_mmio_read32le+0x1c/0x3c (P)
>  regmap_mmio_read+0x40/0x68
>  _regmap_bus_reg_read+0x58/0x9c
>  _regmap_read+0x70/0x1c4
>  _regmap_update_bits+0xe4/0x174
>  regmap_update_bits_base+0x60/0x90
>  imx95_pcie_core_reset+0x78/0xd0
>  imx_pcie_assert_core_reset+0x38/0x50
>  imx_pcie_host_init+0x68/0x4a0
>  dw_pcie_host_init+0x16c/0x500
>  imx_pcie_probe+0x2f4/0x71c
>  platform_probe+0x64/0x100
>  really_probe+0xc8/0x3bc
>  __driver_probe_device+0x84/0x16c
>  driver_probe_device+0x40/0x160
>  __device_attach_driver+0xcc/0x1a0
>  bus_for_each_drv+0x88/0xe4
>  __device_attach_async_helper+0xac/0x108
>  async_run_entry_fn+0x30/0x144
>  process_one_work+0x14c/0x3e0
>  worker_thread+0x2f0/0x3fc
>  kthread+0x128/0x1ec
>  ret_from_fork+0x10/0x20
> 
> Code: aa0003f4 2a0103f3 f9400280 8b334000 (b9400000)
> ---[ end trace 0000000000000000 ]---

Is this series dependent on any other series/patches?

Best regards,
Alexander
-- 
TQ-Systems GmbH | Mühlstraße 2, Gut Delling | 82229 Seefeld, Germany
Amtsgericht München, HRB 105018
Geschäftsführer: Detlef Schneider, Rüdiger Stahl, Stefan Schneider
http://www.tq-group.com/

Re: [PATCH v5 3/7] PCI: imx6: Toggle the cold reset for i.MX95 PCIe

[Frank Li]

On Wed, Apr 09, 2025 at 11:51:53AM +0200, Alexander Stein wrote:
> Hi,
>
> Am Dienstag, 8. April 2025, 04:59:26 CEST schrieb Richard Zhu:
> > Add the cold reset toggle for i.MX95 PCIe to align PHY's power up sequency.
> >
> > Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
> > Reviewed-by: Frank Li <Frank.Li@nxp.com>
> > ---
> >  drivers/pci/controller/dwc/pci-imx6.c | 42 +++++++++++++++++++++++++++
> >  1 file changed, 42 insertions(+)
> >
> > diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
> > index c5871c3d4194..7c60b712480a 100644
> > --- a/drivers/pci/controller/dwc/pci-imx6.c
> > +++ b/drivers/pci/controller/dwc/pci-imx6.c
> > @@ -71,6 +71,9 @@
> >  #define IMX95_SID_MASK				GENMASK(5, 0)
> >  #define IMX95_MAX_LUT				32
> >
> > +#define IMX95_PCIE_RST_CTRL			0x3010
> > +#define IMX95_PCIE_COLD_RST			BIT(0)
> > +
> >  #define to_imx_pcie(x)	dev_get_drvdata((x)->dev)
> >
> >  enum imx_pcie_variants {
> > @@ -773,6 +776,43 @@ static int imx7d_pcie_core_reset(struct imx_pcie *imx_pcie, bool assert)
> >  	return 0;
> >  }
> >
> > +static int imx95_pcie_core_reset(struct imx_pcie *imx_pcie, bool assert)
> > +{
> > +	u32 val;
> > +
> > +	if (assert) {
> > +		/*
> > +		 * From i.MX95 PCIe PHY perspective, the COLD reset toggle
> > +		 * should be complete after power-up by the following sequence.
> > +		 *                 > 10us(at power-up)
> > +		 *                 > 10ns(warm reset)
> > +		 *               |<------------>|
> > +		 *                ______________
> > +		 * phy_reset ____/              \________________
> > +		 *                                   ____________
> > +		 * ref_clk_en_______________________/
> > +		 * Toggle COLD reset aligned with this sequence for i.MX95 PCIe.
> > +		 */
> > +		regmap_set_bits(imx_pcie->iomuxc_gpr, IMX95_PCIE_RST_CTRL,
> > +				IMX95_PCIE_COLD_RST);
> > +		/*
> > +		 * Make sure the write to IMX95_PCIE_RST_CTRL is flushed to the
> > +		 * hardware by doing a read. Otherwise, there is no guarantee
> > +		 * that the write has reached the hardware before udelay().
> > +		 */
> > +		regmap_read_bypassed(imx_pcie->iomuxc_gpr, IMX95_PCIE_RST_CTRL,
> > +				     &val);
> > +		udelay(15);
> > +		regmap_clear_bits(imx_pcie->iomuxc_gpr, IMX95_PCIE_RST_CTRL,
> > +				  IMX95_PCIE_COLD_RST);
> > +		regmap_read_bypassed(imx_pcie->iomuxc_gpr, IMX95_PCIE_RST_CTRL,
> > +				     &val);
> > +		udelay(10);
> > +	}
> > +
> > +	return 0;
> > +}
> > +
> >  static void imx_pcie_assert_core_reset(struct imx_pcie *imx_pcie)
> >  {
> >  	reset_control_assert(imx_pcie->pciephy_reset);
> > @@ -1739,6 +1779,7 @@ static const struct imx_pcie_drvdata drvdata[] = {
> >  		.ltssm_mask = IMX95_PCIE_LTSSM_EN,
> >  		.mode_off[0]  = IMX95_PE0_GEN_CTRL_1,
> >  		.mode_mask[0] = IMX95_PCIE_DEVICE_TYPE,
> > +		.core_reset = imx95_pcie_core_reset,
> >  		.init_phy = imx95_pcie_init_phy,
> >  	},
> >  	[IMX8MQ_EP] = {
> > @@ -1792,6 +1833,7 @@ static const struct imx_pcie_drvdata drvdata[] = {
> >  		.mode_off[0]  = IMX95_PE0_GEN_CTRL_1,
> >  		.mode_mask[0] = IMX95_PCIE_DEVICE_TYPE,
> >  		.init_phy = imx95_pcie_init_phy,
> > +		.core_reset = imx95_pcie_core_reset,
> >  		.epc_features = &imx95_pcie_epc_features,
> >  		.mode = DW_PCIE_EP_TYPE,
> >  	},
> >
>
> This change introduces an invalid memory access on my platform. There is not
> even a PCIe device attached to it.
>
> > imx6q-pcie 4c380000.pcie: host bridge /soc/pcie@4c380000 ranges:
> > imx6q-pcie 4c300000.pcie: host bridge /soc/pcie@4c300000 ranges:
> > imx6q-pcie 4c380000.pcie:       IO 0x088ff00000..0x088fffffff -> 0x0000000000
> > imx6q-pcie 4c300000.pcie:       IO 0x006ff00000..0x006fffffff -> 0x0000000000
> > imx6q-pcie 4c380000.pcie:      MEM 0x0a10000000..0x0a1fffffff -> 0x0010000000
> > imx6q-pcie 4c300000.pcie:      MEM 0x0910000000..0x091fffffff -> 0x0010000000
> > imx6q-pcie 4c380000.pcie: config reg[1] 0x880100000 == cpu 0x880100000
> > ; no fixup was ever needed for this devicetree
> > imx6q-pcie 4c300000.pcie: config reg[1] 0x60100000 == cpu 0x60100000
> > ; no fixup was ever needed for this devicetree
> > Unable to handle kernel paging request at virtual address ffff800081dc5010
> > Unable to handle kernel paging request at virtual address ffff8000821bd010
> > Mem abort info:
> >
> > Mem abort info:
> >   ESR = 0x0000000096000007
> >   ESR = 0x0000000096000007
> >   EC = 0x25: DABT (current EL), IL = 32 bits
> >   EC = 0x25: DABT (current EL), IL = 32 bits
> >
> > fsl_enetc_mdio 0003:01:00.0: enabling device (0000 -> 0002)
> >
> >   SET = 0, FnV = 0
> >   SET = 0, FnV = 0
> >   EA = 0, S1PTW = 0
> >   EA = 0, S1PTW = 0
> >   FSC = 0x07: level 3 translation fault
> >   FSC = 0x07: level 3 translation fault
> >
> > Data abort info:
> >
> > Data abort info:
> >   ISV = 0, ISS = 0x00000007, ISS2 = 0x00000000
> >   ISV = 0, ISS = 0x00000007, ISS2 = 0x00000000
> >   CM = 0, WnR = 0, TnD = 0, TagAccess = 0
> >   CM = 0, WnR = 0, TnD = 0, TagAccess = 0
> >   GCS = 0, Overlay = 0, DirtyBit = 0, Xs = 0
> >   GCS = 0, Overlay = 0, DirtyBit = 0, Xs = 0
> >
> > swapper pgtable: 4k pages, 48-bit VAs, pgdp=0000000091a47000
> > swapper pgtable: 4k pages, 48-bit VAs, pgdp=0000000091a47000
> > [ffff800081dc5010] pgd=1000000092002003
> > [ffff8000821bd010] pgd=1000000092002003
> > , p4d=1000000092002003
> > , p4d=1000000092002003
> > , pud=1000000092003003
> > , pud=1000000092003003
> > , pmd=1000000092008003
> > , pmd=100000009299f403
> > , pte=0000000000000000
> > , pte=0000000000000000
> >
> >
> > Internal error: Oops: 0000000096000007 [#1]  SMP
> > Modules linked in:
> > CPU: 0 UID: 0 PID: 63 Comm: kworker/u24:4 Tainted: G                T
> > 6.15.0-rc1-next-20250409+ #3009 PREEMPT
> > f6bd3cc6346487744ae55f6115e728ff2bc7088b Tainted: [T]=RANDSTRUCT
> > Hardware name: TQ-Systems i.MX95 TQMa95xxSA on MB-SMARC-2 (DT)
> > Workqueue: async async_run_entry_fn
> > pstate: 204000c9 (nzCv daIF +PAN -UAO -TCO -DIT -SSBS BTYPE=--)
> > pc : regmap_mmio_read32le+0x1c/0x3c
> > lr : regmap_mmio_read+0x40/0x68
> > sp : ffff80008223b860
> > x29: ffff80008223b860 x28: ffff00001000c800 x27: ffff8000818679c0
> > x26: ffff000013340410 x25: 0000000000000001 x24: 0000000000000000
> > x23: ffff000012f5e400 x22: ffff80008223b934 x21: ffff80008223b934
> > x20: ffff000012fc4900 x19: 0000000000003010 x18: 00000000a7aa953f
> > x17: 3e2d206666666666 x16: 666631393078302e x15: 2e30303030303030
> > x14: 3139307830204d45 x13: 3030303030303031 x12: 30307830203e2d20
> > x11: 6666666666666631 x10: 393078302e2e3030 x9 : 4d2020202020203a
> > x8 : 656963702e303030 x7 : 205d313236353838 x6 : ffff0000134e0000
> > x5 : 0000000000000000 x4 : 0000000000000000 x3 : ffff8000809bf028
> > x2 : ffff8000809bfb0c x1 : 0000000000003010 x0 : ffff800081dc5010
> >
> > Call trace:
> >  regmap_mmio_read32le+0x1c/0x3c (P)
> >  regmap_mmio_read+0x40/0x68
> >  _regmap_bus_reg_read+0x58/0x9c
> >  _regmap_read+0x70/0x1c4
> >  _regmap_update_bits+0xe4/0x174
> >  regmap_update_bits_base+0x60/0x90
> >  imx95_pcie_core_reset+0x78/0xd0
> >  imx_pcie_assert_core_reset+0x38/0x50
> >  imx_pcie_host_init+0x68/0x4a0
> >  dw_pcie_host_init+0x16c/0x500
> >  imx_pcie_probe+0x2f4/0x71c
> >  platform_probe+0x64/0x100
> >  really_probe+0xc8/0x3bc
> >  __driver_probe_device+0x84/0x16c
> >  driver_probe_device+0x40/0x160
> >  __device_attach_driver+0xcc/0x1a0
> >  bus_for_each_drv+0x88/0xe4
> >  __device_attach_async_helper+0xac/0x108
> >  async_run_entry_fn+0x30/0x144
> >  process_one_work+0x14c/0x3e0
> >  worker_thread+0x2f0/0x3fc
> >  kthread+0x128/0x1ec
> >  ret_from_fork+0x10/0x20
> >
> > Code: aa0003f4 2a0103f3 f9400280 8b334000 (b9400000)
> > ---[ end trace 0000000000000000 ]---
> > note: kworker/u24:4[63] exited with irqs disabled
> > Internal error: Oops: 0000000096000007 [#2]  SMP
> > Modules linked in:
> > note: kworker/u24:4[63] exited with preempt_count 1
> >
> > CPU: 4 UID: 0 PID: 52 Comm: kworker/u24:1 Tainted: G      D         T
> > 6.15.0-rc1-next-20250409+ #3009 PREEMPT
> > f6bd3cc6346487744ae55f6115e728ff2bc7088b Tainted: [D]=DIE, [T]=RANDSTRUCT
> > Hardware name: TQ-Systems i.MX95 TQMa95xxSA on MB-SMARC-2 (DT)
> > Workqueue: async async_run_entry_fn
> > pstate: 204000c9 (nzCv daIF +PAN -UAO -TCO -DIT -SSBS BTYPE=--)
> > pc : regmap_mmio_read32le+0x1c/0x3c
> > lr : regmap_mmio_read+0x40/0x68
> > mmc0: new HS400 Enhanced strobe MMC card at address 0001
> > sp : ffff8000821e3860
> > mmcblk0: mmc0:0001 DG4016 14.7 GiB
> > x29: ffff8000821e3860 x28: ffff00001000c800 x27: ffff8000818679c0
> > mmcblk0boot0: mmc0:0001 DG4016 4.00 MiB
> > x26: ffff00001333fc10 x25: 0000000000000001 x24: 0000000000000000
> > x23: ffff000013895400 x22: ffff8000821e3934 x21: ffff8000821e3934
> > x20: ffff0000134672c0
> > mmcblk0boot1: mmc0:0001 DG4016 4.00 MiB
> >
> >  x19: 0000000000003010 x18: 0000000038868210
> >
> > x17: 3038387830207570 x16: 63203d3d20303030 x15: 3030313038387830
> > x14: 205d315b67657220
> > mmcblk0rpmb: mmc0:0001 DG4016 4.00 MiB, chardev (237:0)
> >
> >  x13: 6565727465636976 x12: 6564207369687420
> >
> > x11: 726f662064656465 x10: 656e207265766520 x9 : 7420726f66206465
> > x8 : 6465656e20726576 x7 : 205d303033353938 x6 : ffff000013371280
> > x5 : 0000000000000000 x4 : 0000000000000000 x3 : ffff8000809bf028
> > x2 : ffff8000809bfb0c x1 : 0000000000003010 x0 : ffff8000821bd010
> >
> > Call trace:
> >  regmap_mmio_read32le+0x1c/0x3c (P)
> >  regmap_mmio_read+0x40/0x68
> >  _regmap_bus_reg_read+0x58/0x9c
> >  _regmap_read+0x70/0x1c4
> >  _regmap_update_bits+0xe4/0x174
> >  regmap_update_bits_base+0x60/0x90
> >  imx95_pcie_core_reset+0x78/0xd0
> >  imx_pcie_assert_core_reset+0x38/0x50
> >  imx_pcie_host_init+0x68/0x4a0
> >  dw_pcie_host_init+0x16c/0x500
> >  imx_pcie_probe+0x2f4/0x71c
> >  platform_probe+0x64/0x100
> >  really_probe+0xc8/0x3bc
> >  __driver_probe_device+0x84/0x16c
> >  driver_probe_device+0x40/0x160
> >  __device_attach_driver+0xcc/0x1a0
> >  bus_for_each_drv+0x88/0xe4
> >  __device_attach_async_helper+0xac/0x108
> >  async_run_entry_fn+0x30/0x144
> >  process_one_work+0x14c/0x3e0
> >  worker_thread+0x2f0/0x3fc
> >  kthread+0x128/0x1ec
> >  ret_from_fork+0x10/0x20
> >
> > Code: aa0003f4 2a0103f3 f9400280 8b334000 (b9400000)
> > ---[ end trace 0000000000000000 ]---
>
> Is this series dependent on any other series/patches?

Please update dts

https://lore.kernel.org/imx/20250314060104.390065-1-hongxing.zhu@nxp.com/
arm64: dts: imx95: Correct the range of PCIe app-reg region

Frank
>
> Best regards,
> Alexander
> --
> TQ-Systems GmbH | Mühlstraße 2, Gut Delling | 82229 Seefeld, Germany
> Amtsgericht München, HRB 105018
> Geschäftsführer: Detlef Schneider, Rüdiger Stahl, Stefan Schneider
> http://www.tq-group.com/
>
>

Re: [PATCH v5 3/7] PCI: imx6: Toggle the cold reset for i.MX95 PCIe

[Alexander Stein]

Am Mittwoch, 9. April 2025, 17:02:43 CEST schrieb Frank Li:
> ********************
> Achtung externe E-Mail: Öffnen Sie Anhänge und Links nur, wenn Sie wissen, dass diese aus einer sicheren Quelle stammen und sicher sind. Leiten Sie die E-Mail im Zweifelsfall zur Prüfung an den IT-Helpdesk weiter.
> Attention external email: Open attachments and links only if you know that they are from a secure source and are safe. In doubt forward the email to the IT-Helpdesk to check it.
> ********************
> 
> On Wed, Apr 09, 2025 at 11:51:53AM +0200, Alexander Stein wrote:
> > Hi,
> >
> > Am Dienstag, 8. April 2025, 04:59:26 CEST schrieb Richard Zhu:
> > > Add the cold reset toggle for i.MX95 PCIe to align PHY's power up sequency.
> > >
> > > Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
> > > Reviewed-by: Frank Li <Frank.Li@nxp.com>
> > > ---
> > >  drivers/pci/controller/dwc/pci-imx6.c | 42 +++++++++++++++++++++++++++
> > >  1 file changed, 42 insertions(+)
> > >
> > > diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
> > > index c5871c3d4194..7c60b712480a 100644
> > > --- a/drivers/pci/controller/dwc/pci-imx6.c
> > > +++ b/drivers/pci/controller/dwc/pci-imx6.c
> > > @@ -71,6 +71,9 @@
> > >  #define IMX95_SID_MASK				GENMASK(5, 0)
> > >  #define IMX95_MAX_LUT				32
> > >
> > > +#define IMX95_PCIE_RST_CTRL			0x3010
> > > +#define IMX95_PCIE_COLD_RST			BIT(0)
> > > +
> > >  #define to_imx_pcie(x)	dev_get_drvdata((x)->dev)
> > >
> > >  enum imx_pcie_variants {
> > > @@ -773,6 +776,43 @@ static int imx7d_pcie_core_reset(struct imx_pcie *imx_pcie, bool assert)
> > >  	return 0;
> > >  }
> > >
> > > +static int imx95_pcie_core_reset(struct imx_pcie *imx_pcie, bool assert)
> > > +{
> > > +	u32 val;
> > > +
> > > +	if (assert) {
> > > +		/*
> > > +		 * From i.MX95 PCIe PHY perspective, the COLD reset toggle
> > > +		 * should be complete after power-up by the following sequence.
> > > +		 *                 > 10us(at power-up)
> > > +		 *                 > 10ns(warm reset)
> > > +		 *               |<------------>|
> > > +		 *                ______________
> > > +		 * phy_reset ____/              \________________
> > > +		 *                                   ____________
> > > +		 * ref_clk_en_______________________/
> > > +		 * Toggle COLD reset aligned with this sequence for i.MX95 PCIe.
> > > +		 */
> > > +		regmap_set_bits(imx_pcie->iomuxc_gpr, IMX95_PCIE_RST_CTRL,
> > > +				IMX95_PCIE_COLD_RST);
> > > +		/*
> > > +		 * Make sure the write to IMX95_PCIE_RST_CTRL is flushed to the
> > > +		 * hardware by doing a read. Otherwise, there is no guarantee
> > > +		 * that the write has reached the hardware before udelay().
> > > +		 */
> > > +		regmap_read_bypassed(imx_pcie->iomuxc_gpr, IMX95_PCIE_RST_CTRL,
> > > +				     &val);
> > > +		udelay(15);
> > > +		regmap_clear_bits(imx_pcie->iomuxc_gpr, IMX95_PCIE_RST_CTRL,
> > > +				  IMX95_PCIE_COLD_RST);
> > > +		regmap_read_bypassed(imx_pcie->iomuxc_gpr, IMX95_PCIE_RST_CTRL,
> > > +				     &val);
> > > +		udelay(10);
> > > +	}
> > > +
> > > +	return 0;
> > > +}
> > > +
> > >  static void imx_pcie_assert_core_reset(struct imx_pcie *imx_pcie)
> > >  {
> > >  	reset_control_assert(imx_pcie->pciephy_reset);
> > > @@ -1739,6 +1779,7 @@ static const struct imx_pcie_drvdata drvdata[] = {
> > >  		.ltssm_mask = IMX95_PCIE_LTSSM_EN,
> > >  		.mode_off[0]  = IMX95_PE0_GEN_CTRL_1,
> > >  		.mode_mask[0] = IMX95_PCIE_DEVICE_TYPE,
> > > +		.core_reset = imx95_pcie_core_reset,
> > >  		.init_phy = imx95_pcie_init_phy,
> > >  	},
> > >  	[IMX8MQ_EP] = {
> > > @@ -1792,6 +1833,7 @@ static const struct imx_pcie_drvdata drvdata[] = {
> > >  		.mode_off[0]  = IMX95_PE0_GEN_CTRL_1,
> > >  		.mode_mask[0] = IMX95_PCIE_DEVICE_TYPE,
> > >  		.init_phy = imx95_pcie_init_phy,
> > > +		.core_reset = imx95_pcie_core_reset,
> > >  		.epc_features = &imx95_pcie_epc_features,
> > >  		.mode = DW_PCIE_EP_TYPE,
> > >  	},
> > >
> >
> > This change introduces an invalid memory access on my platform. There is not
> > even a PCIe device attached to it.
> >
> > > imx6q-pcie 4c380000.pcie: host bridge /soc/pcie@4c380000 ranges:
> > > imx6q-pcie 4c300000.pcie: host bridge /soc/pcie@4c300000 ranges:
> > > imx6q-pcie 4c380000.pcie:       IO 0x088ff00000..0x088fffffff -> 0x0000000000
> > > imx6q-pcie 4c300000.pcie:       IO 0x006ff00000..0x006fffffff -> 0x0000000000
> > > imx6q-pcie 4c380000.pcie:      MEM 0x0a10000000..0x0a1fffffff -> 0x0010000000
> > > imx6q-pcie 4c300000.pcie:      MEM 0x0910000000..0x091fffffff -> 0x0010000000
> > > imx6q-pcie 4c380000.pcie: config reg[1] 0x880100000 == cpu 0x880100000
> > > ; no fixup was ever needed for this devicetree
> > > imx6q-pcie 4c300000.pcie: config reg[1] 0x60100000 == cpu 0x60100000
> > > ; no fixup was ever needed for this devicetree
> > > Unable to handle kernel paging request at virtual address ffff800081dc5010
> > > Unable to handle kernel paging request at virtual address ffff8000821bd010
> > > Mem abort info:
> > >
> > > Mem abort info:
> > >   ESR = 0x0000000096000007
> > >   ESR = 0x0000000096000007
> > >   EC = 0x25: DABT (current EL), IL = 32 bits
> > >   EC = 0x25: DABT (current EL), IL = 32 bits
> > >
> > > fsl_enetc_mdio 0003:01:00.0: enabling device (0000 -> 0002)
> > >
> > >   SET = 0, FnV = 0
> > >   SET = 0, FnV = 0
> > >   EA = 0, S1PTW = 0
> > >   EA = 0, S1PTW = 0
> > >   FSC = 0x07: level 3 translation fault
> > >   FSC = 0x07: level 3 translation fault
> > >
> > > Data abort info:
> > >
> > > Data abort info:
> > >   ISV = 0, ISS = 0x00000007, ISS2 = 0x00000000
> > >   ISV = 0, ISS = 0x00000007, ISS2 = 0x00000000
> > >   CM = 0, WnR = 0, TnD = 0, TagAccess = 0
> > >   CM = 0, WnR = 0, TnD = 0, TagAccess = 0
> > >   GCS = 0, Overlay = 0, DirtyBit = 0, Xs = 0
> > >   GCS = 0, Overlay = 0, DirtyBit = 0, Xs = 0
> > >
> > > swapper pgtable: 4k pages, 48-bit VAs, pgdp=0000000091a47000
> > > swapper pgtable: 4k pages, 48-bit VAs, pgdp=0000000091a47000
> > > [ffff800081dc5010] pgd=1000000092002003
> > > [ffff8000821bd010] pgd=1000000092002003
> > > , p4d=1000000092002003
> > > , p4d=1000000092002003
> > > , pud=1000000092003003
> > > , pud=1000000092003003
> > > , pmd=1000000092008003
> > > , pmd=100000009299f403
> > > , pte=0000000000000000
> > > , pte=0000000000000000
> > >
> > >
> > > Internal error: Oops: 0000000096000007 [#1]  SMP
> > > Modules linked in:
> > > CPU: 0 UID: 0 PID: 63 Comm: kworker/u24:4 Tainted: G                T
> > > 6.15.0-rc1-next-20250409+ #3009 PREEMPT
> > > f6bd3cc6346487744ae55f6115e728ff2bc7088b Tainted: [T]=RANDSTRUCT
> > > Hardware name: TQ-Systems i.MX95 TQMa95xxSA on MB-SMARC-2 (DT)
> > > Workqueue: async async_run_entry_fn
> > > pstate: 204000c9 (nzCv daIF +PAN -UAO -TCO -DIT -SSBS BTYPE=--)
> > > pc : regmap_mmio_read32le+0x1c/0x3c
> > > lr : regmap_mmio_read+0x40/0x68
> > > sp : ffff80008223b860
> > > x29: ffff80008223b860 x28: ffff00001000c800 x27: ffff8000818679c0
> > > x26: ffff000013340410 x25: 0000000000000001 x24: 0000000000000000
> > > x23: ffff000012f5e400 x22: ffff80008223b934 x21: ffff80008223b934
> > > x20: ffff000012fc4900 x19: 0000000000003010 x18: 00000000a7aa953f
> > > x17: 3e2d206666666666 x16: 666631393078302e x15: 2e30303030303030
> > > x14: 3139307830204d45 x13: 3030303030303031 x12: 30307830203e2d20
> > > x11: 6666666666666631 x10: 393078302e2e3030 x9 : 4d2020202020203a
> > > x8 : 656963702e303030 x7 : 205d313236353838 x6 : ffff0000134e0000
> > > x5 : 0000000000000000 x4 : 0000000000000000 x3 : ffff8000809bf028
> > > x2 : ffff8000809bfb0c x1 : 0000000000003010 x0 : ffff800081dc5010
> > >
> > > Call trace:
> > >  regmap_mmio_read32le+0x1c/0x3c (P)
> > >  regmap_mmio_read+0x40/0x68
> > >  _regmap_bus_reg_read+0x58/0x9c
> > >  _regmap_read+0x70/0x1c4
> > >  _regmap_update_bits+0xe4/0x174
> > >  regmap_update_bits_base+0x60/0x90
> > >  imx95_pcie_core_reset+0x78/0xd0
> > >  imx_pcie_assert_core_reset+0x38/0x50
> > >  imx_pcie_host_init+0x68/0x4a0
> > >  dw_pcie_host_init+0x16c/0x500
> > >  imx_pcie_probe+0x2f4/0x71c
> > >  platform_probe+0x64/0x100
> > >  really_probe+0xc8/0x3bc
> > >  __driver_probe_device+0x84/0x16c
> > >  driver_probe_device+0x40/0x160
> > >  __device_attach_driver+0xcc/0x1a0
> > >  bus_for_each_drv+0x88/0xe4
> > >  __device_attach_async_helper+0xac/0x108
> > >  async_run_entry_fn+0x30/0x144
> > >  process_one_work+0x14c/0x3e0
> > >  worker_thread+0x2f0/0x3fc
> > >  kthread+0x128/0x1ec
> > >  ret_from_fork+0x10/0x20
> > >
> > > Code: aa0003f4 2a0103f3 f9400280 8b334000 (b9400000)
> > > ---[ end trace 0000000000000000 ]---
> > > note: kworker/u24:4[63] exited with irqs disabled
> > > Internal error: Oops: 0000000096000007 [#2]  SMP
> > > Modules linked in:
> > > note: kworker/u24:4[63] exited with preempt_count 1
> > >
> > > CPU: 4 UID: 0 PID: 52 Comm: kworker/u24:1 Tainted: G      D         T
> > > 6.15.0-rc1-next-20250409+ #3009 PREEMPT
> > > f6bd3cc6346487744ae55f6115e728ff2bc7088b Tainted: [D]=DIE, [T]=RANDSTRUCT
> > > Hardware name: TQ-Systems i.MX95 TQMa95xxSA on MB-SMARC-2 (DT)
> > > Workqueue: async async_run_entry_fn
> > > pstate: 204000c9 (nzCv daIF +PAN -UAO -TCO -DIT -SSBS BTYPE=--)
> > > pc : regmap_mmio_read32le+0x1c/0x3c
> > > lr : regmap_mmio_read+0x40/0x68
> > > mmc0: new HS400 Enhanced strobe MMC card at address 0001
> > > sp : ffff8000821e3860
> > > mmcblk0: mmc0:0001 DG4016 14.7 GiB
> > > x29: ffff8000821e3860 x28: ffff00001000c800 x27: ffff8000818679c0
> > > mmcblk0boot0: mmc0:0001 DG4016 4.00 MiB
> > > x26: ffff00001333fc10 x25: 0000000000000001 x24: 0000000000000000
> > > x23: ffff000013895400 x22: ffff8000821e3934 x21: ffff8000821e3934
> > > x20: ffff0000134672c0
> > > mmcblk0boot1: mmc0:0001 DG4016 4.00 MiB
> > >
> > >  x19: 0000000000003010 x18: 0000000038868210
> > >
> > > x17: 3038387830207570 x16: 63203d3d20303030 x15: 3030313038387830
> > > x14: 205d315b67657220
> > > mmcblk0rpmb: mmc0:0001 DG4016 4.00 MiB, chardev (237:0)
> > >
> > >  x13: 6565727465636976 x12: 6564207369687420
> > >
> > > x11: 726f662064656465 x10: 656e207265766520 x9 : 7420726f66206465
> > > x8 : 6465656e20726576 x7 : 205d303033353938 x6 : ffff000013371280
> > > x5 : 0000000000000000 x4 : 0000000000000000 x3 : ffff8000809bf028
> > > x2 : ffff8000809bfb0c x1 : 0000000000003010 x0 : ffff8000821bd010
> > >
> > > Call trace:
> > >  regmap_mmio_read32le+0x1c/0x3c (P)
> > >  regmap_mmio_read+0x40/0x68
> > >  _regmap_bus_reg_read+0x58/0x9c
> > >  _regmap_read+0x70/0x1c4
> > >  _regmap_update_bits+0xe4/0x174
> > >  regmap_update_bits_base+0x60/0x90
> > >  imx95_pcie_core_reset+0x78/0xd0
> > >  imx_pcie_assert_core_reset+0x38/0x50
> > >  imx_pcie_host_init+0x68/0x4a0
> > >  dw_pcie_host_init+0x16c/0x500
> > >  imx_pcie_probe+0x2f4/0x71c
> > >  platform_probe+0x64/0x100
> > >  really_probe+0xc8/0x3bc
> > >  __driver_probe_device+0x84/0x16c
> > >  driver_probe_device+0x40/0x160
> > >  __device_attach_driver+0xcc/0x1a0
> > >  bus_for_each_drv+0x88/0xe4
> > >  __device_attach_async_helper+0xac/0x108
> > >  async_run_entry_fn+0x30/0x144
> > >  process_one_work+0x14c/0x3e0
> > >  worker_thread+0x2f0/0x3fc
> > >  kthread+0x128/0x1ec
> > >  ret_from_fork+0x10/0x20
> > >
> > > Code: aa0003f4 2a0103f3 f9400280 8b334000 (b9400000)
> > > ---[ end trace 0000000000000000 ]---
> >
> > Is this series dependent on any other series/patches?
> 
> Please update dts
> 
> https://lore.kernel.org/imx/20250314060104.390065-1-hongxing.zhu@nxp.com/
> arm64: dts: imx95: Correct the range of PCIe app-reg region

This should have been mentioned in the cover letter that there are some
dependencies.
Anyway, the series looks okay. Even though I have no documentation
regarding the erratas.

Best regards,
Alexander
-- 
TQ-Systems GmbH | Mühlstraße 2, Gut Delling | 82229 Seefeld, Germany
Amtsgericht München, HRB 105018
Geschäftsführer: Detlef Schneider, Rüdiger Stahl, Stefan Schneider
http://www.tq-group.com/

Re: [PATCH v5 2/7] PCI: imx6: Skip one dw_pcie_wait_for_link() in workaround link training

[ALOK TIWARI]

On 08-04-2025 08:29, Richard Zhu wrote:
> Remove one reduntant dw_pcie_wait_for_link() in link traning workaround
> because common framework already do that.
> 

typo: reduntant -> redundant ,traning ->training

> Suggested-by: Manivannan Sadhasivam<manivannan.sadhasivam@linaro.org>
> Signed-off-by: Richard Zhu<hongxing.zhu@nxp.com>
> Reviewed-by: Frank Li<Frank.Li@nxp.com>

Thanks,
Alok

Re: [PATCH v5 2/7] PCI: imx6: Skip one dw_pcie_wait_for_link() in workaround link training

[Manivannan Sadhasivam]

On Tue, Apr 08, 2025 at 10:59:25AM +0800, Richard Zhu wrote:
> Remove one reduntant dw_pcie_wait_for_link() in link traning workaround
> because common framework already do that.
> 
> Suggested-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>

Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>

- Mani

> Reviewed-by: Frank Li <Frank.Li@nxp.com>
> ---
>  drivers/pci/controller/dwc/pci-imx6.c | 15 ++++-----------
>  1 file changed, 4 insertions(+), 11 deletions(-)
> 
> diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
> index a4c0714c6468..c5871c3d4194 100644
> --- a/drivers/pci/controller/dwc/pci-imx6.c
> +++ b/drivers/pci/controller/dwc/pci-imx6.c
> @@ -881,11 +881,11 @@ static int imx_pcie_start_link(struct dw_pcie *pci)
>  	/* Start LTSSM. */
>  	imx_pcie_ltssm_enable(dev);
>  
> -	ret = dw_pcie_wait_for_link(pci);
> -	if (ret)
> -		goto err_reset_phy;
> -
>  	if (pci->max_link_speed > 1) {
> +		ret = dw_pcie_wait_for_link(pci);
> +		if (ret)
> +			goto err_reset_phy;
> +
>  		/* Allow faster modes after the link is up */
>  		dw_pcie_dbi_ro_wr_en(pci);
>  		tmp = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP);
> @@ -907,17 +907,10 @@ static int imx_pcie_start_link(struct dw_pcie *pci)
>  			dev_err(dev, "Failed to bring link up!\n");
>  			goto err_reset_phy;
>  		}
> -
> -		/* Make sure link training is finished as well! */
> -		ret = dw_pcie_wait_for_link(pci);
> -		if (ret)
> -			goto err_reset_phy;
>  	} else {
>  		dev_info(dev, "Link: Only Gen1 is enabled\n");
>  	}
>  
> -	tmp = dw_pcie_readw_dbi(pci, offset + PCI_EXP_LNKSTA);
> -	dev_info(dev, "Link up, Gen%i\n", tmp & PCI_EXP_LNKSTA_CLS);
>  	return 0;
>  
>  err_reset_phy:
> -- 
> 2.37.1
> 

-- 
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Re: [PATCH v5 3/7] PCI: imx6: Toggle the cold reset for i.MX95 PCIe

[Manivannan Sadhasivam]

On Tue, Apr 08, 2025 at 10:59:26AM +0800, Richard Zhu wrote:
> Add the cold reset toggle for i.MX95 PCIe to align PHY's power up sequency.

Please avoid spelling mistakes in the commit messages.

> 
> Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>

Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>

- Mani

> Reviewed-by: Frank Li <Frank.Li@nxp.com>
> ---
>  drivers/pci/controller/dwc/pci-imx6.c | 42 +++++++++++++++++++++++++++
>  1 file changed, 42 insertions(+)
> 
> diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
> index c5871c3d4194..7c60b712480a 100644
> --- a/drivers/pci/controller/dwc/pci-imx6.c
> +++ b/drivers/pci/controller/dwc/pci-imx6.c
> @@ -71,6 +71,9 @@
>  #define IMX95_SID_MASK				GENMASK(5, 0)
>  #define IMX95_MAX_LUT				32
>  
> +#define IMX95_PCIE_RST_CTRL			0x3010
> +#define IMX95_PCIE_COLD_RST			BIT(0)
> +
>  #define to_imx_pcie(x)	dev_get_drvdata((x)->dev)
>  
>  enum imx_pcie_variants {
> @@ -773,6 +776,43 @@ static int imx7d_pcie_core_reset(struct imx_pcie *imx_pcie, bool assert)
>  	return 0;
>  }
>  
> +static int imx95_pcie_core_reset(struct imx_pcie *imx_pcie, bool assert)
> +{
> +	u32 val;
> +
> +	if (assert) {
> +		/*
> +		 * From i.MX95 PCIe PHY perspective, the COLD reset toggle
> +		 * should be complete after power-up by the following sequence.
> +		 *                 > 10us(at power-up)
> +		 *                 > 10ns(warm reset)
> +		 *               |<------------>|
> +		 *                ______________
> +		 * phy_reset ____/              \________________
> +		 *                                   ____________
> +		 * ref_clk_en_______________________/
> +		 * Toggle COLD reset aligned with this sequence for i.MX95 PCIe.
> +		 */
> +		regmap_set_bits(imx_pcie->iomuxc_gpr, IMX95_PCIE_RST_CTRL,
> +				IMX95_PCIE_COLD_RST);
> +		/*
> +		 * Make sure the write to IMX95_PCIE_RST_CTRL is flushed to the
> +		 * hardware by doing a read. Otherwise, there is no guarantee
> +		 * that the write has reached the hardware before udelay().
> +		 */
> +		regmap_read_bypassed(imx_pcie->iomuxc_gpr, IMX95_PCIE_RST_CTRL,
> +				     &val);
> +		udelay(15);
> +		regmap_clear_bits(imx_pcie->iomuxc_gpr, IMX95_PCIE_RST_CTRL,
> +				  IMX95_PCIE_COLD_RST);
> +		regmap_read_bypassed(imx_pcie->iomuxc_gpr, IMX95_PCIE_RST_CTRL,
> +				     &val);
> +		udelay(10);
> +	}
> +
> +	return 0;
> +}
> +
>  static void imx_pcie_assert_core_reset(struct imx_pcie *imx_pcie)
>  {
>  	reset_control_assert(imx_pcie->pciephy_reset);
> @@ -1739,6 +1779,7 @@ static const struct imx_pcie_drvdata drvdata[] = {
>  		.ltssm_mask = IMX95_PCIE_LTSSM_EN,
>  		.mode_off[0]  = IMX95_PE0_GEN_CTRL_1,
>  		.mode_mask[0] = IMX95_PCIE_DEVICE_TYPE,
> +		.core_reset = imx95_pcie_core_reset,
>  		.init_phy = imx95_pcie_init_phy,
>  	},
>  	[IMX8MQ_EP] = {
> @@ -1792,6 +1833,7 @@ static const struct imx_pcie_drvdata drvdata[] = {
>  		.mode_off[0]  = IMX95_PE0_GEN_CTRL_1,
>  		.mode_mask[0] = IMX95_PCIE_DEVICE_TYPE,
>  		.init_phy = imx95_pcie_init_phy,
> +		.core_reset = imx95_pcie_core_reset,
>  		.epc_features = &imx95_pcie_epc_features,
>  		.mode = DW_PCIE_EP_TYPE,
>  	},
> -- 
> 2.37.1
> 

-- 
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Re: [PATCH v5 4/7] PCI: imx6: Workaround i.MX95 PCIe may not exit L23 ready

[Manivannan Sadhasivam]

On Tue, Apr 08, 2025 at 10:59:27AM +0800, Richard Zhu wrote:
> ERR051624: The Controller Without Vaux Cannot Exit L23 Ready Through Beacon
> or PERST# De-assertion
> 
> When the auxiliary power is not available, the controller cannot exit from
> L23 Ready with beacon or PERST# de-assertion when main power is not
> removed.
> 
> Workaround: Set SS_RW_REG_1[SYS_AUX_PWR_DET] to 1.
> 

Please do not post next version without concluding the review comments. It just
wastes reviewers time and is not a good practice.

You haven't resolved my comments on v3. So I'm not going to review this one.

- Mani

> Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
> Reviewed-by: Frank Li <Frank.Li@nxp.com>
> ---
>  drivers/pci/controller/dwc/pci-imx6.c | 15 +++++++++++++++
>  1 file changed, 15 insertions(+)
> 
> diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
> index 7c60b712480a..016b86add959 100644
> --- a/drivers/pci/controller/dwc/pci-imx6.c
> +++ b/drivers/pci/controller/dwc/pci-imx6.c
> @@ -48,6 +48,8 @@
>  #define IMX95_PCIE_SS_RW_REG_0			0xf0
>  #define IMX95_PCIE_REF_CLKEN			BIT(23)
>  #define IMX95_PCIE_PHY_CR_PARA_SEL		BIT(9)
> +#define IMX95_PCIE_SS_RW_REG_1			0xf4
> +#define IMX95_PCIE_SYS_AUX_PWR_DET		BIT(31)
>  
>  #define IMX95_PE0_GEN_CTRL_1			0x1050
>  #define IMX95_PCIE_DEVICE_TYPE			GENMASK(3, 0)
> @@ -227,6 +229,19 @@ static unsigned int imx_pcie_grp_offset(const struct imx_pcie *imx_pcie)
>  
>  static int imx95_pcie_init_phy(struct imx_pcie *imx_pcie)
>  {
> +	/*
> +	 * ERR051624: The Controller Without Vaux Cannot Exit L23 Ready
> +	 * Through Beacon or PERST# De-assertion
> +	 *
> +	 * When the auxiliary power is not available, the controller
> +	 * cannot exit from L23 Ready with beacon or PERST# de-assertion
> +	 * when main power is not removed.
> +	 *
> +	 * Workaround: Set SS_RW_REG_1[SYS_AUX_PWR_DET] to 1.
> +	 */
> +	regmap_set_bits(imx_pcie->iomuxc_gpr, IMX95_PCIE_SS_RW_REG_1,
> +			IMX95_PCIE_SYS_AUX_PWR_DET);
> +
>  	regmap_update_bits(imx_pcie->iomuxc_gpr,
>  			IMX95_PCIE_SS_RW_REG_0,
>  			IMX95_PCIE_PHY_CR_PARA_SEL,
> -- 
> 2.37.1
> 

-- 
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Re: [PATCH v5 6/7] PCI: imx6: Add PLL clock lock check for i.MX95 PCIe

[Manivannan Sadhasivam]

On Tue, Apr 08, 2025 at 10:59:29AM +0800, Richard Zhu wrote:
> Add PLL clock lock check for i.MX95 PCIe.
> 
> Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
> Reviewed-by: Frank Li <Frank.Li@nxp.com>
> ---
>  drivers/pci/controller/dwc/pci-imx6.c | 28 +++++++++++++++++++++++++--
>  1 file changed, 26 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
> index 7dcc9d88740d..c1d128ec255d 100644
> --- a/drivers/pci/controller/dwc/pci-imx6.c
> +++ b/drivers/pci/controller/dwc/pci-imx6.c
> @@ -45,6 +45,9 @@
>  #define IMX95_PCIE_PHY_GEN_CTRL			0x0
>  #define IMX95_PCIE_REF_USE_PAD			BIT(17)
>  
> +#define IMX95_PCIE_PHY_MPLLA_CTRL		0x10
> +#define IMX95_PCIE_PHY_MPLL_STATE		BIT(30)
> +
>  #define IMX95_PCIE_SS_RW_REG_0			0xf0
>  #define IMX95_PCIE_REF_CLKEN			BIT(23)
>  #define IMX95_PCIE_PHY_CR_PARA_SEL		BIT(9)
> @@ -479,6 +482,23 @@ static void imx7d_pcie_wait_for_phy_pll_lock(struct imx_pcie *imx_pcie)
>  		dev_err(dev, "PCIe PLL lock timeout\n");
>  }
>  
> +static int imx95_pcie_wait_for_phy_pll_lock(struct imx_pcie *imx_pcie)
> +{
> +	u32 val;
> +	struct device *dev = imx_pcie->pci->dev;
> +
> +	if (regmap_read_poll_timeout(imx_pcie->iomuxc_gpr,
> +				     IMX95_PCIE_PHY_MPLLA_CTRL, val,
> +				     val & IMX95_PCIE_PHY_MPLL_STATE,
> +				     PHY_PLL_LOCK_WAIT_USLEEP_MAX,
> +				     PHY_PLL_LOCK_WAIT_TIMEOUT)) {
> +		dev_err(dev, "PCIe PLL lock timeout\n");
> +		return -ETIMEDOUT;
> +	}
> +
> +	return 0;
> +}
> +
>  static int imx_setup_phy_mpll(struct imx_pcie *imx_pcie)
>  {
>  	unsigned long phy_rate = 0;
> @@ -824,6 +844,8 @@ static int imx95_pcie_core_reset(struct imx_pcie *imx_pcie, bool assert)
>  		regmap_read_bypassed(imx_pcie->iomuxc_gpr, IMX95_PCIE_RST_CTRL,
>  				     &val);
>  		udelay(10);
> +	} else {
> +		return imx95_pcie_wait_for_phy_pll_lock(imx_pcie);

Is this PLL lock related to COLD_RESET? It doesn't look like it. If unrelated,
it should be called wherever required. imx95_pcie_core_reset() is supposed to
only assert/deassert the COLD_RESET.

If related, please explain how.

- Mani

-- 
மணிவண்ணன் சதாசிவம்

RE: [PATCH v5 6/7] PCI: imx6: Add PLL clock lock check for i.MX95 PCIe

[Hongxing Zhu]

> -----Original Message-----
> From: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> Sent: 2025年4月13日 23:33
> To: Hongxing Zhu <hongxing.zhu@nxp.com>
> Cc: Frank Li <frank.li@nxp.com>; l.stach@pengutronix.de;
> lpieralisi@kernel.org; kw@linux.com; robh@kernel.org;
> bhelgaas@google.com; shawnguo@kernel.org; s.hauer@pengutronix.de;
> kernel@pengutronix.de; festevam@gmail.com; linux-pci@vger.kernel.org;
> linux-arm-kernel@lists.infradead.org; imx@lists.linux.dev;
> linux-kernel@vger.kernel.org
> Subject: Re: [PATCH v5 6/7] PCI: imx6: Add PLL clock lock check for i.MX95
> PCIe
> 
> On Tue, Apr 08, 2025 at 10:59:29AM +0800, Richard Zhu wrote:
> > Add PLL clock lock check for i.MX95 PCIe.
> >
> > Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
> > Reviewed-by: Frank Li <Frank.Li@nxp.com>
> > ---
> >  drivers/pci/controller/dwc/pci-imx6.c | 28
> > +++++++++++++++++++++++++--
> >  1 file changed, 26 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/pci/controller/dwc/pci-imx6.c
> > b/drivers/pci/controller/dwc/pci-imx6.c
> > index 7dcc9d88740d..c1d128ec255d 100644
> > --- a/drivers/pci/controller/dwc/pci-imx6.c
> > +++ b/drivers/pci/controller/dwc/pci-imx6.c
> > @@ -45,6 +45,9 @@
> >  #define IMX95_PCIE_PHY_GEN_CTRL			0x0
> >  #define IMX95_PCIE_REF_USE_PAD			BIT(17)
> >
> > +#define IMX95_PCIE_PHY_MPLLA_CTRL		0x10
> > +#define IMX95_PCIE_PHY_MPLL_STATE		BIT(30)
> > +
> >  #define IMX95_PCIE_SS_RW_REG_0			0xf0
> >  #define IMX95_PCIE_REF_CLKEN			BIT(23)
> >  #define IMX95_PCIE_PHY_CR_PARA_SEL		BIT(9)
> > @@ -479,6 +482,23 @@ static void
> imx7d_pcie_wait_for_phy_pll_lock(struct imx_pcie *imx_pcie)
> >  		dev_err(dev, "PCIe PLL lock timeout\n");  }
> >
> > +static int imx95_pcie_wait_for_phy_pll_lock(struct imx_pcie
> > +*imx_pcie) {
> > +	u32 val;
> > +	struct device *dev = imx_pcie->pci->dev;
> > +
> > +	if (regmap_read_poll_timeout(imx_pcie->iomuxc_gpr,
> > +				     IMX95_PCIE_PHY_MPLLA_CTRL, val,
> > +				     val & IMX95_PCIE_PHY_MPLL_STATE,
> > +				     PHY_PLL_LOCK_WAIT_USLEEP_MAX,
> > +				     PHY_PLL_LOCK_WAIT_TIMEOUT)) {
> > +		dev_err(dev, "PCIe PLL lock timeout\n");
> > +		return -ETIMEDOUT;
> > +	}
> > +
> > +	return 0;
> > +}
> > +
> >  static int imx_setup_phy_mpll(struct imx_pcie *imx_pcie)  {
> >  	unsigned long phy_rate = 0;
> > @@ -824,6 +844,8 @@ static int imx95_pcie_core_reset(struct imx_pcie
> *imx_pcie, bool assert)
> >  		regmap_read_bypassed(imx_pcie->iomuxc_gpr,
> IMX95_PCIE_RST_CTRL,
> >  				     &val);
> >  		udelay(10);
> > +	} else {
> > +		return imx95_pcie_wait_for_phy_pll_lock(imx_pcie);
> 
> Is this PLL lock related to COLD_RESET? It doesn't look like it. If unrelated, it
> should be called wherever required. imx95_pcie_core_reset() is supposed to
> only assert/deassert the COLD_RESET.
> 
> If related, please explain how.
Thanks for your kindly review.
To make sure the HW state is correct to continue the sequential initializations.
The PLL lock or not check would be kicked off after the COLD_RESET is
 de-asserted for i.MX95 PCIe.
So, the PLL lock check is added at the end of de-assertion in
 imx95_pcie_core_reset() function.

Best Regards
Richard Zhu
> 
> - Mani
> 
> --
> மணிவண்ணன் சதாசிவம்

RE: [PATCH v5 3/7] PCI: imx6: Toggle the cold reset for i.MX95 PCIe

[Hongxing Zhu]

> -----Original Message-----
> From: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> Sent: 2025年4月13日 23:18
> To: Hongxing Zhu <hongxing.zhu@nxp.com>
> Cc: Frank Li <frank.li@nxp.com>; l.stach@pengutronix.de;
> lpieralisi@kernel.org; kw@linux.com; robh@kernel.org;
> bhelgaas@google.com; shawnguo@kernel.org; s.hauer@pengutronix.de;
> kernel@pengutronix.de; festevam@gmail.com; linux-pci@vger.kernel.org;
> linux-arm-kernel@lists.infradead.org; imx@lists.linux.dev;
> linux-kernel@vger.kernel.org
> Subject: Re: [PATCH v5 3/7] PCI: imx6: Toggle the cold reset for i.MX95 PCIe
> 
> On Tue, Apr 08, 2025 at 10:59:26AM +0800, Richard Zhu wrote:
> > Add the cold reset toggle for i.MX95 PCIe to align PHY's power up sequency.
> 
> Please avoid spelling mistakes in the commit messages.
> 
Okay, would be replaced by the following one.
Add a cold reset toggle for the i.MX95 PCIe to align the PHY's power-up
 sequence.

> >
> > Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
> 
> Reviewed-by: Manivannan Sadhasivam
> <manivannan.sadhasivam@linaro.org>
> 
Thanks.
Best Regards
Richard

> - Mani
> 
> > Reviewed-by: Frank Li <Frank.Li@nxp.com>
> > ---
> >  drivers/pci/controller/dwc/pci-imx6.c | 42
> > +++++++++++++++++++++++++++
> >  1 file changed, 42 insertions(+)
> >
> > diff --git a/drivers/pci/controller/dwc/pci-imx6.c
> > b/drivers/pci/controller/dwc/pci-imx6.c
> > index c5871c3d4194..7c60b712480a 100644
> > --- a/drivers/pci/controller/dwc/pci-imx6.c
> > +++ b/drivers/pci/controller/dwc/pci-imx6.c
> > @@ -71,6 +71,9 @@
> >  #define IMX95_SID_MASK				GENMASK(5, 0)
> >  #define IMX95_MAX_LUT				32
> >
> > +#define IMX95_PCIE_RST_CTRL			0x3010
> > +#define IMX95_PCIE_COLD_RST			BIT(0)
> > +
> >  #define to_imx_pcie(x)	dev_get_drvdata((x)->dev)
> >
> >  enum imx_pcie_variants {
> > @@ -773,6 +776,43 @@ static int imx7d_pcie_core_reset(struct imx_pcie
> *imx_pcie, bool assert)
> >  	return 0;
> >  }
> >
> > +static int imx95_pcie_core_reset(struct imx_pcie *imx_pcie, bool
> > +assert) {
> > +	u32 val;
> > +
> > +	if (assert) {
> > +		/*
> > +		 * From i.MX95 PCIe PHY perspective, the COLD reset toggle
> > +		 * should be complete after power-up by the following sequence.
> > +		 *                 > 10us(at power-up)
> > +		 *                 > 10ns(warm reset)
> > +		 *               |<------------>|
> > +		 *                ______________
> > +		 * phy_reset ____/              \________________
> > +		 *                                   ____________
> > +		 * ref_clk_en_______________________/
> > +		 * Toggle COLD reset aligned with this sequence for i.MX95 PCIe.
> > +		 */
> > +		regmap_set_bits(imx_pcie->iomuxc_gpr, IMX95_PCIE_RST_CTRL,
> > +				IMX95_PCIE_COLD_RST);
> > +		/*
> > +		 * Make sure the write to IMX95_PCIE_RST_CTRL is flushed to the
> > +		 * hardware by doing a read. Otherwise, there is no guarantee
> > +		 * that the write has reached the hardware before udelay().
> > +		 */
> > +		regmap_read_bypassed(imx_pcie->iomuxc_gpr,
> IMX95_PCIE_RST_CTRL,
> > +				     &val);
> > +		udelay(15);
> > +		regmap_clear_bits(imx_pcie->iomuxc_gpr, IMX95_PCIE_RST_CTRL,
> > +				  IMX95_PCIE_COLD_RST);
> > +		regmap_read_bypassed(imx_pcie->iomuxc_gpr,
> IMX95_PCIE_RST_CTRL,
> > +				     &val);
> > +		udelay(10);
> > +	}
> > +
> > +	return 0;
> > +}
> > +
> >  static void imx_pcie_assert_core_reset(struct imx_pcie *imx_pcie)  {
> >  	reset_control_assert(imx_pcie->pciephy_reset);
> > @@ -1739,6 +1779,7 @@ static const struct imx_pcie_drvdata drvdata[] = {
> >  		.ltssm_mask = IMX95_PCIE_LTSSM_EN,
> >  		.mode_off[0]  = IMX95_PE0_GEN_CTRL_1,
> >  		.mode_mask[0] = IMX95_PCIE_DEVICE_TYPE,
> > +		.core_reset = imx95_pcie_core_reset,
> >  		.init_phy = imx95_pcie_init_phy,
> >  	},
> >  	[IMX8MQ_EP] = {
> > @@ -1792,6 +1833,7 @@ static const struct imx_pcie_drvdata drvdata[] = {
> >  		.mode_off[0]  = IMX95_PE0_GEN_CTRL_1,
> >  		.mode_mask[0] = IMX95_PCIE_DEVICE_TYPE,
> >  		.init_phy = imx95_pcie_init_phy,
> > +		.core_reset = imx95_pcie_core_reset,
> >  		.epc_features = &imx95_pcie_epc_features,
> >  		.mode = DW_PCIE_EP_TYPE,
> >  	},
> > --
> > 2.37.1
> >
> 
> --
> மணிவண்ணன் சதாசிவம்

Re: [PATCH v5 6/7] PCI: imx6: Add PLL clock lock check for i.MX95 PCIe

[Manivannan Sadhasivam]

On Mon, Apr 14, 2025 at 03:16:46AM +0000, Hongxing Zhu wrote:
> > -----Original Message-----
> > From: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> > Sent: 2025年4月13日 23:33
> > To: Hongxing Zhu <hongxing.zhu@nxp.com>
> > Cc: Frank Li <frank.li@nxp.com>; l.stach@pengutronix.de;
> > lpieralisi@kernel.org; kw@linux.com; robh@kernel.org;
> > bhelgaas@google.com; shawnguo@kernel.org; s.hauer@pengutronix.de;
> > kernel@pengutronix.de; festevam@gmail.com; linux-pci@vger.kernel.org;
> > linux-arm-kernel@lists.infradead.org; imx@lists.linux.dev;
> > linux-kernel@vger.kernel.org
> > Subject: Re: [PATCH v5 6/7] PCI: imx6: Add PLL clock lock check for i.MX95
> > PCIe
> > 
> > On Tue, Apr 08, 2025 at 10:59:29AM +0800, Richard Zhu wrote:
> > > Add PLL clock lock check for i.MX95 PCIe.
> > >
> > > Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
> > > Reviewed-by: Frank Li <Frank.Li@nxp.com>
> > > ---
> > >  drivers/pci/controller/dwc/pci-imx6.c | 28
> > > +++++++++++++++++++++++++--
> > >  1 file changed, 26 insertions(+), 2 deletions(-)
> > >
> > > diff --git a/drivers/pci/controller/dwc/pci-imx6.c
> > > b/drivers/pci/controller/dwc/pci-imx6.c
> > > index 7dcc9d88740d..c1d128ec255d 100644
> > > --- a/drivers/pci/controller/dwc/pci-imx6.c
> > > +++ b/drivers/pci/controller/dwc/pci-imx6.c
> > > @@ -45,6 +45,9 @@
> > >  #define IMX95_PCIE_PHY_GEN_CTRL			0x0
> > >  #define IMX95_PCIE_REF_USE_PAD			BIT(17)
> > >
> > > +#define IMX95_PCIE_PHY_MPLLA_CTRL		0x10
> > > +#define IMX95_PCIE_PHY_MPLL_STATE		BIT(30)
> > > +
> > >  #define IMX95_PCIE_SS_RW_REG_0			0xf0
> > >  #define IMX95_PCIE_REF_CLKEN			BIT(23)
> > >  #define IMX95_PCIE_PHY_CR_PARA_SEL		BIT(9)
> > > @@ -479,6 +482,23 @@ static void
> > imx7d_pcie_wait_for_phy_pll_lock(struct imx_pcie *imx_pcie)
> > >  		dev_err(dev, "PCIe PLL lock timeout\n");  }
> > >
> > > +static int imx95_pcie_wait_for_phy_pll_lock(struct imx_pcie
> > > +*imx_pcie) {
> > > +	u32 val;
> > > +	struct device *dev = imx_pcie->pci->dev;
> > > +
> > > +	if (regmap_read_poll_timeout(imx_pcie->iomuxc_gpr,
> > > +				     IMX95_PCIE_PHY_MPLLA_CTRL, val,
> > > +				     val & IMX95_PCIE_PHY_MPLL_STATE,
> > > +				     PHY_PLL_LOCK_WAIT_USLEEP_MAX,
> > > +				     PHY_PLL_LOCK_WAIT_TIMEOUT)) {
> > > +		dev_err(dev, "PCIe PLL lock timeout\n");
> > > +		return -ETIMEDOUT;
> > > +	}
> > > +
> > > +	return 0;
> > > +}
> > > +
> > >  static int imx_setup_phy_mpll(struct imx_pcie *imx_pcie)  {
> > >  	unsigned long phy_rate = 0;
> > > @@ -824,6 +844,8 @@ static int imx95_pcie_core_reset(struct imx_pcie
> > *imx_pcie, bool assert)
> > >  		regmap_read_bypassed(imx_pcie->iomuxc_gpr,
> > IMX95_PCIE_RST_CTRL,
> > >  				     &val);
> > >  		udelay(10);
> > > +	} else {
> > > +		return imx95_pcie_wait_for_phy_pll_lock(imx_pcie);
> > 
> > Is this PLL lock related to COLD_RESET? It doesn't look like it. If unrelated, it
> > should be called wherever required. imx95_pcie_core_reset() is supposed to
> > only assert/deassert the COLD_RESET.
> > 
> > If related, please explain how.
> Thanks for your kindly review.
> To make sure the HW state is correct to continue the sequential initializations.
> The PLL lock or not check would be kicked off after the COLD_RESET is
>  de-asserted for i.MX95 PCIe.
> So, the PLL lock check is added at the end of de-assertion in
>  imx95_pcie_core_reset() function.
> 

But imx95_pcie_core_reset() is not doing anything for deassert other than
waiting for PLL lock. Hence my question.

- Mani

-- 
மணிவண்ணன் சதாசிவம்

RE: [PATCH v5 6/7] PCI: imx6: Add PLL clock lock check for i.MX95 PCIe

[Hongxing Zhu]

> -----Original Message-----
> From: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> Sent: 2025年4月15日 15:21
> To: Hongxing Zhu <hongxing.zhu@nxp.com>
> Cc: Frank Li <frank.li@nxp.com>; l.stach@pengutronix.de; lpieralisi@kernel.org;
> kw@linux.com; robh@kernel.org; bhelgaas@google.com;
> shawnguo@kernel.org; s.hauer@pengutronix.de; kernel@pengutronix.de;
> festevam@gmail.com; linux-pci@vger.kernel.org;
> linux-arm-kernel@lists.infradead.org; imx@lists.linux.dev;
> linux-kernel@vger.kernel.org
> Subject: Re: [PATCH v5 6/7] PCI: imx6: Add PLL clock lock check for i.MX95 PCIe
> 
> On Mon, Apr 14, 2025 at 03:16:46AM +0000, Hongxing Zhu wrote:
> > > -----Original Message-----
> > > From: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> > > Sent: 2025年4月13日 23:33
> > > To: Hongxing Zhu <hongxing.zhu@nxp.com>
> > > Cc: Frank Li <frank.li@nxp.com>; l.stach@pengutronix.de;
> > > lpieralisi@kernel.org; kw@linux.com; robh@kernel.org;
> > > bhelgaas@google.com; shawnguo@kernel.org; s.hauer@pengutronix.de;
> > > kernel@pengutronix.de; festevam@gmail.com;
> > > linux-pci@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> > > imx@lists.linux.dev; linux-kernel@vger.kernel.org
> > > Subject: Re: [PATCH v5 6/7] PCI: imx6: Add PLL clock lock check for
> > > i.MX95 PCIe
> > >
> > > On Tue, Apr 08, 2025 at 10:59:29AM +0800, Richard Zhu wrote:
> > > > Add PLL clock lock check for i.MX95 PCIe.
> > > >
> > > > Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
> > > > Reviewed-by: Frank Li <Frank.Li@nxp.com>
> > > > ---
> > > >  drivers/pci/controller/dwc/pci-imx6.c | 28
> > > > +++++++++++++++++++++++++--
> > > >  1 file changed, 26 insertions(+), 2 deletions(-)
> > > >
> > > > diff --git a/drivers/pci/controller/dwc/pci-imx6.c
> > > > b/drivers/pci/controller/dwc/pci-imx6.c
> > > > index 7dcc9d88740d..c1d128ec255d 100644
> > > > --- a/drivers/pci/controller/dwc/pci-imx6.c
> > > > +++ b/drivers/pci/controller/dwc/pci-imx6.c
> > > > @@ -45,6 +45,9 @@
> > > >  #define IMX95_PCIE_PHY_GEN_CTRL			0x0
> > > >  #define IMX95_PCIE_REF_USE_PAD			BIT(17)
> > > >
> > > > +#define IMX95_PCIE_PHY_MPLLA_CTRL		0x10
> > > > +#define IMX95_PCIE_PHY_MPLL_STATE		BIT(30)
> > > > +
> > > >  #define IMX95_PCIE_SS_RW_REG_0			0xf0
> > > >  #define IMX95_PCIE_REF_CLKEN			BIT(23)
> > > >  #define IMX95_PCIE_PHY_CR_PARA_SEL		BIT(9)
> > > > @@ -479,6 +482,23 @@ static void
> > > imx7d_pcie_wait_for_phy_pll_lock(struct imx_pcie *imx_pcie)
> > > >  		dev_err(dev, "PCIe PLL lock timeout\n");  }
> > > >
> > > > +static int imx95_pcie_wait_for_phy_pll_lock(struct imx_pcie
> > > > +*imx_pcie) {
> > > > +	u32 val;
> > > > +	struct device *dev = imx_pcie->pci->dev;
> > > > +
> > > > +	if (regmap_read_poll_timeout(imx_pcie->iomuxc_gpr,
> > > > +				     IMX95_PCIE_PHY_MPLLA_CTRL, val,
> > > > +				     val & IMX95_PCIE_PHY_MPLL_STATE,
> > > > +				     PHY_PLL_LOCK_WAIT_USLEEP_MAX,
> > > > +				     PHY_PLL_LOCK_WAIT_TIMEOUT)) {
> > > > +		dev_err(dev, "PCIe PLL lock timeout\n");
> > > > +		return -ETIMEDOUT;
> > > > +	}
> > > > +
> > > > +	return 0;
> > > > +}
> > > > +
> > > >  static int imx_setup_phy_mpll(struct imx_pcie *imx_pcie)  {
> > > >  	unsigned long phy_rate = 0;
> > > > @@ -824,6 +844,8 @@ static int imx95_pcie_core_reset(struct
> > > > imx_pcie
> > > *imx_pcie, bool assert)
> > > >  		regmap_read_bypassed(imx_pcie->iomuxc_gpr,
> > > IMX95_PCIE_RST_CTRL,
> > > >  				     &val);
> > > >  		udelay(10);
> > > > +	} else {
> > > > +		return imx95_pcie_wait_for_phy_pll_lock(imx_pcie);
> > >
> > > Is this PLL lock related to COLD_RESET? It doesn't look like it. If
> > > unrelated, it should be called wherever required.
> > > imx95_pcie_core_reset() is supposed to only assert/deassert the
> COLD_RESET.
> > >
> > > If related, please explain how.
> > Thanks for your kindly review.
> > To make sure the HW state is correct to continue the sequential initializations.
> > The PLL lock or not check would be kicked off after the COLD_RESET is
> > de-asserted for i.MX95 PCIe.
> > So, the PLL lock check is added at the end of de-assertion in
> >  imx95_pcie_core_reset() function.
> >
> 
> But imx95_pcie_core_reset() is not doing anything for deassert other than
> waiting for PLL lock. Hence my question.
Okay, I see.
How about add one more callback (e.x wait_pll_lock) and do the pll lock
 check after imx_pcie_deassert_core_reset()?

Best Regards
Richard Zhu
> 
> - Mani
> 
> --
> மணிவண்ணன் சதாசிவம்