From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.0 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,NICE_REPLY_A,SPF_HELO_NONE,SPF_PASS, USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 83E6BC12002 for ; Thu, 15 Jul 2021 03:11:12 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 430D761396 for ; Thu, 15 Jul 2021 03:11:12 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 430D761396 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:Date: Message-ID:From:References:Cc:To:Subject:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=3uXxG590VoU4jY8LlEvuAklhB44tWH5XI200qlFzoXs=; b=0Ud7XSrS8K0ANFrgDRbypTVy1q 2xVFiqi/egdyEeo3LJgPGcRWXZfKTpS+MqX0TPJCqeXiMoJi7ID+olgf+uNaporj7CNOTjw9l6AB2 B305NF6cxjJavbENBoARPO+g/amYVjsUAKSZqC/N8+tb45hUx+VRwA1CECMbeZ7RuKy7n/2Aaw72e 9WK/qJ4tUtSeYETc4yZdQqbzl41A/g4k8hUoeWUHHZiX+tUSqDQyuX4uDVNVm0dajw8kkAORm8iBO 9YagP5pXKBAebnqqYXfZGCQ+GrbjW+svYGKoyReEpPMdCIq/ye+6xD0wbV49uJyYFuWoztx9VItnK gvXYscAw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1m3rkc-00Gyue-Fe; Thu, 15 Jul 2021 03:09:26 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1m3rkX-00GytJ-JU for linux-arm-kernel@lists.infradead.org; Thu, 15 Jul 2021 03:09:23 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 1203AD6E; Wed, 14 Jul 2021 20:09:15 -0700 (PDT) Received: from [10.163.66.71] (unknown [10.163.66.71]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 859693F7D8; Wed, 14 Jul 2021 20:09:11 -0700 (PDT) Subject: Re: [PATCH 5/5] coresight: trbe: Prohibit tracing while handling an IRQ To: Suzuki K Poulose , linux-arm-kernel@lists.infradead.org Cc: coresight@lists.linaro.org, linux-kernel@vger.kernel.org, al.grant@arm.com, leo.yan@linaro.org, mathieu.poirier@linaro.org, mike.leach@linaro.org, peterz@infradead.org, Tamas.Zsoldos@arm.com, will@kernel.org References: <20210712113830.2803257-1-suzuki.poulose@arm.com> <20210712113830.2803257-6-suzuki.poulose@arm.com> From: Anshuman Khandual Message-ID: <1837b3ae-cc0b-d4ba-7d26-1debdc60c016@arm.com> Date: Thu, 15 Jul 2021 08:39:59 +0530 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: <20210712113830.2803257-6-suzuki.poulose@arm.com> Content-Language: en-US X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210714_200921_816046_234D67D9 X-CRM114-Status: GOOD ( 36.34 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org A small nit. Paragraphs in the commit message do not seem to be aligned properly to a maximum 75 characters width. On 7/12/21 5:08 PM, Suzuki K Poulose wrote: > When the TRBE generates an IRQ, we stop the TRBE, collect the trace > and then reprogram the TRBE with the updated buffer pointers in case > of a spurious IRQ. We might also leave the TRBE disabled, on an > overflow interrupt, without touching the ETE. This means the > the ETE is only disabled when the event is disabled later (via irq_work). > This is incorrect, as the ETE trace is still ON without actually being > captured and may be routed to the ATB. I had an assumption that when the TRBE is stopped, ETE would also stop implicitly given that the trace packets are not being accepted anymore. But if that assumption does not always hold true, then yes trace must be stopped upon a TRBE IRQ. > > So, we move the CPU into trace prohibited state (for all exception > levels) upon entering the IRQ handler. The state is restored before > enabling the TRBE back. Otherwise the trace remains prohibited. > Since, the ETM/ETE driver controls the TRFCR_EL1 per session, > (from commit "coresight: etm4x: Use Trace Filtering controls dynamically") commit SHA ID ? > the tracing can be restored/enabled back when the event is rescheduled > in. Makes sense. > > Fixes: 3fbf7f011f24 ("coresight: sink: Add TRBE driver") > Cc: Anshuman Khandual > Cc: Mathieu Poirier > Cc: Mike Leach > Cc: Leo Yan > Signed-off-by: Suzuki K Poulose > --- > drivers/hwtracing/coresight/coresight-trbe.c | 43 ++++++++++++++++++-- > 1 file changed, 40 insertions(+), 3 deletions(-) > > diff --git a/drivers/hwtracing/coresight/coresight-trbe.c b/drivers/hwtracing/coresight/coresight-trbe.c > index c0c264264427..e4d88e0de2a8 100644 > --- a/drivers/hwtracing/coresight/coresight-trbe.c > +++ b/drivers/hwtracing/coresight/coresight-trbe.c > @@ -83,6 +83,31 @@ struct trbe_drvdata { > struct platform_device *pdev; > }; > > +static inline void write_trfcr(u64 val) > +{ > + write_sysreg_s(val, SYS_TRFCR_EL1); > + isb(); > +} > + There is another instance of write_trfcr() in coresight-etm4x-core.c and some other writes into SYS_TRFCR_EL1 elsewhere. write_trfcr() should be factored out and moved to a common place. > +/* > + * Prohibit the CPU tracing at all ELs, in preparation to collect > + * the trace buffer. > + * > + * Returns the original value of the trfcr for restoring later. > + */ > +static u64 cpu_prohibit_tracing(void) > +{ > + u64 trfcr = read_sysreg_s(SYS_TRFCR_EL1); > + > + write_trfcr(trfcr & ~(TRFCR_ELx_ExTRE | TRFCR_ELx_E0TRE)); > + return trfcr; > +} This also should be factored out along with etm4x_prohibit_trace() usage and moved to a common header instead. > + > +static void cpu_restore_tracing(u64 trfcr) > +{ > + write_trfcr(trfcr); > +} > + > static int trbe_alloc_node(struct perf_event *event) > { > if (event->cpu == -1) > @@ -681,7 +706,7 @@ static int arm_trbe_disable(struct coresight_device *csdev) > return 0; > } > > -static void trbe_handle_spurious(struct perf_output_handle *handle) > +static void trbe_handle_spurious(struct perf_output_handle *handle, u64 trfcr) > { > struct trbe_buf *buf = etm_perf_sink_config(handle); > > @@ -691,6 +716,7 @@ static void trbe_handle_spurious(struct perf_output_handle *handle) > trbe_drain_and_disable_local(); > return; > } A small comment here would be great because this will be the only IRQ handler path, where it actually restores the tracing back. > + cpu_restore_tracing(trfcr); > trbe_enable_hw(buf); > } > > @@ -760,7 +786,18 @@ static irqreturn_t arm_trbe_irq_handler(int irq, void *dev) > struct perf_output_handle **handle_ptr = dev; > struct perf_output_handle *handle = *handle_ptr; > enum trbe_fault_action act; > - u64 status; > + u64 status, trfcr; > + > + /* > + * Prohibit the tracing, while we process this. We turn > + * things back right, if we get to enabling the TRBE > + * back again. Otherwise, the tracing still remains > + * prohibited, until the perf event state changes > + * or another event is scheduled. This ensures that > + * the trace is not generated when it cannot be > + * captured. > + */ Right. But a small nit though. Please keep the comments here formatted and aligned with the existing ones. > + trfcr = cpu_prohibit_tracing(); > > /* > * Ensure the trace is visible to the CPUs and > @@ -791,7 +828,7 @@ static irqreturn_t arm_trbe_irq_handler(int irq, void *dev) > trbe_handle_overflow(handle); > break; > case TRBE_FAULT_ACT_SPURIOUS: > - trbe_handle_spurious(handle); > + trbe_handle_spurious(handle, trfcr); > break; > case TRBE_FAULT_ACT_FATAL: > trbe_stop_and_truncate_event(handle); > But stopping the trace (even though from a sink IRQ handler) is a source device action. Should not this be done via a new coresight_ops_source callback instead ? _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel