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From: tomasz.figa@gmail.com (Tomasz Figa)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH] clk: samsung: pll: Use new registration method for PLL6552 and PLL6553
Date: Wed, 21 Aug 2013 02:33:21 +0200	[thread overview]
Message-ID: <1856348.DCxTucbm8V@flatron> (raw)
In-Reply-To: <20130820002258.4443.34197@quantum>

This patch modifies PLL6552 and PLL6553 clock drivers to use recently
added common Samsung PLL registration method.

Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
---
 drivers/clk/samsung/clk-pll.c | 105 +++++-------------------------------------
 drivers/clk/samsung/clk-pll.h |   6 +--
 2 files changed, 13 insertions(+), 98 deletions(-)

diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c
index 0775554..7572d1d 100644
--- a/drivers/clk/samsung/clk-pll.c
+++ b/drivers/clk/samsung/clk-pll.c
@@ -441,9 +441,6 @@ struct clk * __init samsung_clk_register_pll46xx(const char *name,
  * PLL6552 Clock Type
  */
 
-#define PLL6552_LOCK_REG	0x00
-#define PLL6552_CON_REG		0x0c
-
 #define PLL6552_MDIV_MASK	0x3ff
 #define PLL6552_PDIV_MASK	0x3f
 #define PLL6552_SDIV_MASK	0x7
@@ -451,21 +448,14 @@ struct clk * __init samsung_clk_register_pll46xx(const char *name,
 #define PLL6552_PDIV_SHIFT	8
 #define PLL6552_SDIV_SHIFT	0
 
-struct samsung_clk_pll6552 {
-	struct clk_hw hw;
-	void __iomem *reg_base;
-};
-
-#define to_clk_pll6552(_hw) container_of(_hw, struct samsung_clk_pll6552, hw)
-
 static unsigned long samsung_pll6552_recalc_rate(struct clk_hw *hw,
 						unsigned long parent_rate)
 {
-	struct samsung_clk_pll6552 *pll = to_clk_pll6552(hw);
+	struct samsung_clk_pll *pll = to_clk_pll(hw);
 	u32 mdiv, pdiv, sdiv, pll_con;
 	u64 fvco = parent_rate;
 
-	pll_con = __raw_readl(pll->reg_base + PLL6552_CON_REG);
+	pll_con = __raw_readl(pll->con_reg);
 	mdiv = (pll_con >> PLL6552_MDIV_SHIFT) & PLL6552_MDIV_MASK;
 	pdiv = (pll_con >> PLL6552_PDIV_SHIFT) & PLL6552_PDIV_MASK;
 	sdiv = (pll_con >> PLL6552_SDIV_SHIFT) & PLL6552_SDIV_MASK;
@@ -480,48 +470,10 @@ static const struct clk_ops samsung_pll6552_clk_ops = {
 	.recalc_rate = samsung_pll6552_recalc_rate,
 };
 
-struct clk * __init samsung_clk_register_pll6552(const char *name,
-					const char *pname, void __iomem *base)
-{
-	struct samsung_clk_pll6552 *pll;
-	struct clk *clk;
-	struct clk_init_data init;
-
-	pll = kzalloc(sizeof(*pll), GFP_KERNEL);
-	if (!pll) {
-		pr_err("%s: could not allocate pll clk %s\n", __func__, name);
-		return NULL;
-	}
-
-	init.name = name;
-	init.ops = &samsung_pll6552_clk_ops;
-	init.parent_names = &pname;
-	init.num_parents = 1;
-
-	pll->hw.init = &init;
-	pll->reg_base = base;
-
-	clk = clk_register(NULL, &pll->hw);
-	if (IS_ERR(clk)) {
-		pr_err("%s: failed to register pll clock %s\n", __func__,
-				name);
-		kfree(pll);
-	}
-
-	if (clk_register_clkdev(clk, name, NULL))
-		pr_err("%s: failed to register lookup for %s", __func__, name);
-
-	return clk;
-}
-
 /*
  * PLL6553 Clock Type
  */
 
-#define PLL6553_LOCK_REG	0x00
-#define PLL6553_CON0_REG	0x0c
-#define PLL6553_CON1_REG	0x10
-
 #define PLL6553_MDIV_MASK	0xff
 #define PLL6553_PDIV_MASK	0x3f
 #define PLL6553_SDIV_MASK	0x7
@@ -531,22 +483,15 @@ struct clk * __init samsung_clk_register_pll6552(const char *name,
 #define PLL6553_SDIV_SHIFT	0
 #define PLL6553_KDIV_SHIFT	0
 
-struct samsung_clk_pll6553 {
-	struct clk_hw hw;
-	void __iomem *reg_base;
-};
-
-#define to_clk_pll6553(_hw) container_of(_hw, struct samsung_clk_pll6553, hw)
-
 static unsigned long samsung_pll6553_recalc_rate(struct clk_hw *hw,
 						unsigned long parent_rate)
 {
-	struct samsung_clk_pll6553 *pll = to_clk_pll6553(hw);
+	struct samsung_clk_pll *pll = to_clk_pll(hw);
 	u32 mdiv, pdiv, sdiv, kdiv, pll_con0, pll_con1;
 	u64 fvco = parent_rate;
 
-	pll_con0 = __raw_readl(pll->reg_base + PLL6553_CON0_REG);
-	pll_con1 = __raw_readl(pll->reg_base + PLL6553_CON1_REG);
+	pll_con0 = __raw_readl(pll->con_reg);
+	pll_con1 = __raw_readl(pll->con_reg + 0x4);
 	mdiv = (pll_con0 >> PLL6553_MDIV_SHIFT) & PLL6553_MDIV_MASK;
 	pdiv = (pll_con0 >> PLL6553_PDIV_SHIFT) & PLL6553_PDIV_MASK;
 	sdiv = (pll_con0 >> PLL6553_SDIV_SHIFT) & PLL6553_SDIV_MASK;
@@ -563,40 +508,6 @@ static const struct clk_ops samsung_pll6553_clk_ops = {
 	.recalc_rate = samsung_pll6553_recalc_rate,
 };
 
-struct clk * __init samsung_clk_register_pll6553(const char *name,
-					const char *pname, void __iomem *base)
-{
-	struct samsung_clk_pll6553 *pll;
-	struct clk *clk;
-	struct clk_init_data init;
-
-	pll = kzalloc(sizeof(*pll), GFP_KERNEL);
-	if (!pll) {
-		pr_err("%s: could not allocate pll clk %s\n", __func__, name);
-		return NULL;
-	}
-
-	init.name = name;
-	init.ops = &samsung_pll6553_clk_ops;
-	init.parent_names = &pname;
-	init.num_parents = 1;
-
-	pll->hw.init = &init;
-	pll->reg_base = base;
-
-	clk = clk_register(NULL, &pll->hw);
-	if (IS_ERR(clk)) {
-		pr_err("%s: failed to register pll clock %s\n", __func__,
-				name);
-		kfree(pll);
-	}
-
-	if (clk_register_clkdev(clk, name, NULL))
-		pr_err("%s: failed to register lookup for %s", __func__, name);
-
-	return clk;
-}
-
 /*
  * PLL2550x Clock Type
  */
@@ -732,6 +643,12 @@ static void __init _samsung_clk_register_pll(struct samsung_pll_clock *pll_clk,
 		else
 			init.ops = &samsung_pll36xx_clk_ops;
 		break;
+	case pll_6552:
+		init.ops = &samsung_pll6552_clk_ops;
+		break;
+	case pll_6553:
+		init.ops = &samsung_pll6553_clk_ops;
+		break;
 	default:
 		pr_warn("%s: Unknown pll type for pll clk %s\n",
 			__func__, pll_clk->name);
diff --git a/drivers/clk/samsung/clk-pll.h b/drivers/clk/samsung/clk-pll.h
index 2f70e88..cd11037 100644
--- a/drivers/clk/samsung/clk-pll.h
+++ b/drivers/clk/samsung/clk-pll.h
@@ -17,6 +17,8 @@ enum samsung_pll_type {
 	pll_36xx,
 	pll_2550,
 	pll_2650,
+	pll_6552,
+	pll_6553,
 };
 
 #define PLL_35XX_RATE(_rate, _m, _p, _s)			\
@@ -64,10 +66,6 @@ extern struct clk * __init samsung_clk_register_pll45xx(const char *name,
 extern struct clk * __init samsung_clk_register_pll46xx(const char *name,
 			const char *pname, const void __iomem *con_reg,
 			enum pll46xx_type type);
-extern struct clk *samsung_clk_register_pll6552(const char *name,
-			const char *pname, void __iomem *base);
-extern struct clk *samsung_clk_register_pll6553(const char *name,
-			const char *pname, void __iomem *base);
 extern struct clk * __init samsung_clk_register_pll2550x(const char *name,
 			const char *pname, const void __iomem *reg_base,
 			const unsigned long offset);
-- 
1.8.3.2

  parent reply	other threads:[~2013-08-21  0:33 UTC|newest]

Thread overview: 45+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2013-07-22 23:49 [PATCH v2 0/8] Common Clock Framework support for Samsung S3C64xx Tomasz Figa
2013-07-22 23:49 ` [PATCH v2 1/8] clk: mux: Add support for read-only muxes Tomasz Figa
2013-07-23 11:22   ` Sergei Shtylyov
2013-07-23 11:25     ` Tomasz Figa
2013-07-27 12:41   ` Tomasz Figa
2013-08-02 21:46     ` Mike Turquette
2013-07-22 23:49 ` [PATCH v2 2/8] clk: samsung: pll: Add support for PLL6552 and PLL6553 Tomasz Figa
2013-07-23 23:52   ` [PATCH v3 " Tomasz Figa
2013-07-28 12:30     ` Mark Brown
2013-07-28 12:38       ` Tomasz Figa
2013-08-02 22:53         ` Mike Turquette
2013-07-22 23:49 ` [PATCH v2 3/8] clk: samsung: Add clock driver for S3C64xx SoCs Tomasz Figa
2013-07-23 23:55   ` [PATCH v3 " Tomasz Figa
2013-07-22 23:49 ` [PATCH v2 4/8] ARM: SAMSUNG: Add soc_is_s3c6400/s3c6410 macros Tomasz Figa
2013-07-22 23:49 ` [PATCH v2 5/8] ARM: s3c64xx: dma: Use clk_prepare_enable/clk_disable_unprepare Tomasz Figa
2013-07-28 12:32   ` Mark Brown
2013-07-22 23:49 ` [PATCH v2 6/8] usb: host: ohci-s3c2410 " Tomasz Figa
2013-07-23  0:15   ` Fabio Estevam
2013-07-23  0:44     ` Tomasz Figa
2013-07-31 18:58   ` Tomasz Figa
2013-07-31 20:44     ` Alan Stern
2013-08-01  7:45       ` Greg KH
2013-07-22 23:49 ` [PATCH v2 7/8] ARM: s3c64xx: Migrate clock handling to Common Clock Framework Tomasz Figa
2013-07-22 23:49 ` [PATCH v2 8/8] ARM: s3c64xx: Remove old clock management code Tomasz Figa
2013-07-24 12:20 ` [PATCH v2 0/8] Common Clock Framework support for Samsung S3C64xx Kukjin Kim
2013-08-05 17:01 ` Kukjin Kim
2013-08-05 18:06   ` Mike Turquette
2013-08-05 18:13     ` Kukjin Kim
2013-08-05 19:02       ` Mike Turquette
2013-08-05 23:42         ` Tomasz Figa
2013-08-06 19:47           ` Mike Turquette
2013-08-06 22:06             ` Tomasz Figa
2013-08-06 22:11               ` Kukjin Kim
2013-08-06 22:13                 ` Tomasz Figa
2013-08-16 10:44     ` Tomasz Figa
2013-08-16 21:02       ` Mike Turquette
2013-08-16 21:15         ` Tomasz Figa
2013-08-17 10:30           ` Kukjin Kim
2013-08-20  0:22             ` Mike Turquette
2013-08-20  7:09               ` Kukjin Kim
2013-08-25 17:19                 ` Kukjin Kim
2013-08-21  0:33               ` Tomasz Figa [this message]
2013-08-27  1:14                 ` [PATCH] clk: samsung: pll: Use new registration method for PLL6552 and PLL6553 Mike Turquette
2013-08-27 17:16                   ` Kukjin Kim
2013-08-27 23:45                     ` Mike Turquette

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