From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7F12FCDB482 for ; Tue, 17 Oct 2023 09:37:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Content-ID:In-Reply-To: References:Message-ID:Date:Subject:CC:To:From:Reply-To:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=ro0gTP2Q4iel9u1HbB+THkAgXWa5YmpGPh/q5CxjqmY=; b=4sZruc6AdnzGrB pg+UAk5skfe8/sDGJfc4z7IfkiayoU9RCxyVTHbwZzQnTTKxWSBuGPuGFjcAcgRZufsDMS6USP2E7 nzLF2OnC6Xot0A7XT1au8OtdNiZJO4/hBAOOJvyhcOl9hhpEWTCSWfyZ47n02DdrW5xZSCEDN4wHq dxnG+YUjOwXHqYptkMpUIEg6Sj96GCmq68yD2tHShj4oKEsg2XQPm1KcIS38oNvww0ymf1T8Y4+4I KjPL59r1iClosYGetBonxJ/1l1ajPH3kDm8VpQYqP8GaWglIWPHlrik+id5Jr3moJJhZosNsHEy3P vpNjnB6zzoeSmBMb8IPg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qsgVq-00BqQj-01; Tue, 17 Oct 2023 09:37:18 +0000 Received: from mailgw01.mediatek.com ([216.200.240.184]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1qsgVm-00BqQ3-27; Tue, 17 Oct 2023 09:37:16 +0000 X-UUID: bcbc53746cd011ee9b7791016c24628a-20231017 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=MIME-Version:Content-Transfer-Encoding:Content-ID:Content-Type:In-Reply-To:References:Message-ID:Date:Subject:CC:To:From; bh=78zvHmVJDqPh6bKsTWvw2eU3Qjh+vk0JFAZ4tDlj2KI=; b=l0C3voWlcmsVxq9oqmZWVnT1sBQqJCyId31ZNWdogsSEDnrLBclDPrgzMD+ill5qTWOvL6+H+DOhZZLzXwNYm4EsVfXccBsxRfY8npnaomc8+dvoUNQ5sa3tZvjvw0nCKAaUur35mOf7WshBuSxPExBNW4oppc2jBvRlg20ymFE=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.32,REQID:09ba9252-7281-4b75-9beb-f0ce88200488,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:5f78ec9,CLOUDID:3a162215-4929-4845-9571-38c601e9c3c9,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:11|1,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1,SPR: NO,DKR:0,DKP:0,BRR:0,BRE:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR,TF_CID_SPAM_ULN X-UUID: bcbc53746cd011ee9b7791016c24628a-20231017 Received: from mtkmbs13n2.mediatek.inc [(172.21.101.108)] by mailgw01.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1846369573; Tue, 17 Oct 2023 02:37:07 -0700 Received: from mtkmbs10n1.mediatek.inc (172.21.101.34) by mtkmbs13n1.mediatek.inc (172.21.101.193) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Tue, 17 Oct 2023 17:36:30 +0800 Received: from APC01-SG2-obe.outbound.protection.outlook.com (172.21.101.237) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Tue, 17 Oct 2023 17:36:30 +0800 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=M0D4kbuR/Gofwt132lwHB/1iDOkWoaJ95g7qNZVHcWSTXJWSdfYHtHwZ3HSxmaezHhJiraAIjpqXwp7QhST3FQcqlHzgXUuz10r0kYOYteKJ2KznMbrchNRd04CiYA4j0RsALK4Yc7Vfqys0ACB8VJ1VekN/kuM49NFRR4ERJF7fxfjDoG6enUrjWVGo84mFrlQyPxjExguUX9lZZrAT58vaGAbRKs+ISohTUKRfn7HOjKIMptaKBaE5K2nReJqH0SV9C2FGp+EGJWmV2lf1EHaHSyL7ap+Aw05a8q1zZPlTbZJlLcFua1oz8oDEEzBw1+ueBCmgqVlIoRg8YzqzLQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=78zvHmVJDqPh6bKsTWvw2eU3Qjh+vk0JFAZ4tDlj2KI=; b=ECySybcioEapzJO0n+/3PNenfTKoF6xPf5TJwMjFbL8HsmrfSTTmNJ2Z/vknkQqHb0pGd69t3aX+iIsUAD/xlpBmyvqQZ33ux/YwWxTpYMX3ASSFbNtCiaTzkqZ3pCuDQhNIu6tt2jWrb0CFfz/Lcu5Nav8T/vXttDRdU3H6uHXM5s/UTpHTM0k1tsaq5TetYi7bA3sOoXs7LLxL5WrMuNK5oAsg3OMhGdghsq82sjR/G+opTtHvsFQzmN4mNevgC+5HR1BXGKX54uPC462Ur7yDbCiZNwWNMrXbfLSfOpRjeQJxw3hEPN4qgYaTu4+qmtPRC16xuXQdtoYNjW2yEA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=mediatek.com; dmarc=pass action=none header.from=mediatek.com; dkim=pass header.d=mediatek.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mediateko365.onmicrosoft.com; s=selector2-mediateko365-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=78zvHmVJDqPh6bKsTWvw2eU3Qjh+vk0JFAZ4tDlj2KI=; b=sItE9wKwuwymFRxtldDEgz7f1zSedQkyY64MKeAHSdkp+ytpz8vBw68fCVLqHn37lmVNEDUzaMXPzvaY8DBDpYuGL5kwDu2BxR/VhDr3VXAHzX+ZBFrP+vzd96mxp9w5iFq1PzelSrUZ6gajC9BimTP/NfBeu0gCmohgRD6+CDU= Received: from TYZPR03MB6624.apcprd03.prod.outlook.com (2603:1096:400:1f4::13) by TYZPR03MB7637.apcprd03.prod.outlook.com (2603:1096:400:41f::6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6886.35; Tue, 17 Oct 2023 09:36:28 +0000 Received: from TYZPR03MB6624.apcprd03.prod.outlook.com ([fe80::9c2c:c08a:212f:e984]) by TYZPR03MB6624.apcprd03.prod.outlook.com ([fe80::9c2c:c08a:212f:e984%7]) with mapi id 15.20.6886.034; Tue, 17 Oct 2023 09:36:28 +0000 From: =?utf-8?B?Q0sgSHUgKOiDoeS/iuWFiSk=?= To: =?utf-8?B?U2hhd24gU3VuZyAo5a6L5a2d6KyZKQ==?= , "matthias.bgg@gmail.com" , "angelogioacchino.delregno@collabora.com" , "robh+dt@kernel.org" , "krzysztof.kozlowski+dt@linaro.org" CC: =?utf-8?B?WW9uZ3FpYW5nIE5pdSAo54mb5rC45by6KQ==?= , "linux-kernel@vger.kernel.org" , "linux-mediatek@lists.infradead.org" , "chunkuang.hu@kernel.org" , =?utf-8?B?SmFzb24tSkggTGluICjmnpfnnb/npaUp?= , "devicetree@vger.kernel.org" , =?utf-8?B?TmFuY3kgTGluICjmnpfmrKPonqIp?= , =?utf-8?B?TW91ZHkgSG8gKOS9leWul+WOnyk=?= , "daniel@ffwll.ch" , "p.zabel@pengutronix.de" , "mchehab@kernel.org" , "dri-devel@lists.freedesktop.org" , =?utf-8?B?TmF0aGFuIEx1ICjlkYLmnbHpnJYp?= , "airlied@gmail.com" , "sean@poorly.run" , "hverkuil-cisco@xs4all.nl" , "linux-arm-kernel@lists.infradead.org" , "fshao@chromium.org" , "johnson.wang@mediatek.corp-partner.google.com" Subject: Re: [PATCH v8 17/23] drm/mediatek: Support MT8188 Padding in display driver Thread-Topic: [PATCH v8 17/23] drm/mediatek: Support MT8188 Padding in display driver Thread-Index: AQHaAB1FF3SJV5hojUez30lhqx2z+rBNupKA Date: Tue, 17 Oct 2023 09:36:28 +0000 Message-ID: <185a903fa3d2e99d02c35cb167f71955afd21e6c.camel@mediatek.com> References: <20231016104010.3270-1-shawn.sung@mediatek.com> <20231016104010.3270-18-shawn.sung@mediatek.com> In-Reply-To: <20231016104010.3270-18-shawn.sung@mediatek.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=mediatek.com; x-ms-publictraffictype: Email x-ms-traffictypediagnostic: TYZPR03MB6624:EE_|TYZPR03MB7637:EE_ x-ms-office365-filtering-correlation-id: 42c77c68-45be-4d10-30d4-08dbcef489fe x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: F5DzgiQrnI+ry+l1G+4v4jD95w95BL0GAxuQxMeTp7cTrFQFyZIFNMunbizYKNj87amkfseI5bUiaShJPAwyah5YqaGSjQyY4/R+jVLkaxNhLG66oinK9KuoZZ3pXIX6cm48j5D0v+secIRtf32iFN9JwDpYFrBvyK6cIV7XVWFJDLc78rXIftd6/oGqgINCBm6WjDpsPxDO8XU8CBDQXSdeh7YimOWsnnpQzc8GammSZYMQJB9PHZrdbqWK+448e3xfDv/yaM4b1nHkomaSWZ5tRqrhN0+vdsyhitbCQ3EQjje9FPKDvW5jqblH+cmKg+9N4TbRTQvHgAHC5sL15WdplpyjJUYyspc/n27w7WjcSZIjCjF1LxsRs7Y4MDcF/P5ZjqfnRlolU+zyhj1WC3Ox8bvqrExkmSOx6c6ieOlTaJlDRk8t9k4Qvrjv0GxxX4k5HXA6zRq1HA12qhvoYK2b4CAT9NghNEhZZcgre8uBGhYyeurO5x/dCMLnhIIFDQV39/NPF2BX/26bEHPZNmbbEqkqVO0Ql6BJajTiDEmA3nwO0b7LP1DHwXtE4ko/PZs7hCoZPcx1MnWhjNZsDpHYY25WNysqhJal7qWB13syPHGF/ehrvCihTGMbdb7kMiutTRq7eGQ5myLpk5U7bctiCljJmEnz4ofJNibIxcE= x-forefront-antispam-report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:TYZPR03MB6624.apcprd03.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230031)(396003)(366004)(376002)(136003)(39860400002)(346002)(230922051799003)(186009)(64100799003)(451199024)(1800799009)(2616005)(26005)(38070700005)(8676002)(8936002)(4326008)(71200400001)(66899024)(38100700002)(5660300002)(83380400001)(122000001)(41300700001)(478600001)(2906002)(6486002)(86362001)(4001150100001)(7416002)(110136005)(85182001)(316002)(6512007)(6506007)(66946007)(66556008)(66476007)(66446008)(64756008)(36756003)(54906003)(76116006);DIR:OUT;SFP:1102; x-ms-exchange-antispam-messagedata-chunkcount: 1 x-ms-exchange-antispam-messagedata-0: =?utf-8?B?TUpFRFd2Z0pOa3RQUFpuWkZKYzY5VGFZMndJL2VQa3ZibFhCVE54d3lUclZz?= =?utf-8?B?UUJDY21hRENqTU4yRDhoWVZ3bE9uQzFRMnZZNzZ4U2VYZzhyWTRPQ3pMSXM0?= =?utf-8?B?aG03WHUrOVF4dmNNdVpJaitMbGJWa2ZRc2YxWHAzL2tqelBzVnJuR3p2c2Zo?= =?utf-8?B?UWR0S3hsTkJYbldHa0tGK1J2NTZxRlVFVHRLWTRBa1BjVDhGTEpZYUNZUktH?= =?utf-8?B?UFgzZ1AraEhPVnZHTHl3VmJxYkliY1NDTHZEWVJqUEEzOFdOR0JOeG0wTEwy?= =?utf-8?B?TFRlNDdpUUNQNzNWd0V3V0xIaVU2RS9yTGg5eTNrSHd4ZEJEUHQ4QTBnMGVJ?= =?utf-8?B?MXQwbEwyUFpoQmNickYwVEF5QjJUUnk1U0o1RVZTY0dKUzVuSTRRVXp2ZGJ1?= =?utf-8?B?VGN6Q2dxckNyamdaVGkrSmhPN3RrWXR5SGNRQ1FJUTViWU9sNm5hdnI4TXVa?= =?utf-8?B?b3dsTC9yK3NjUzZoeExoWEFsUDE2QjBZbDY2WWxBMFlKTEY5TmJvZnJkaGRL?= =?utf-8?B?dFJFMnRxcENidi9QaWlvSzB5MHV6WjlGUDdxTzd1VFhvUS92S2xadjY4ZUxU?= =?utf-8?B?a2RTb2FqQitxM0FXWjZ6bzBIa3Yzay9ubXdyVXNYN1VqdU9YWmt6V1JiOTgx?= =?utf-8?B?YXVLYlIrUFJoWFBoNGh2WHlsVlV6ZzlMa2FQMk9Pdk5URHZidldNKzdmdGJr?= =?utf-8?B?Und2M0hjZGVhVG9OaTlSbXRlYWdkK1FHMkxBSEo3S09xKzhKdm5IWklkdDZu?= =?utf-8?B?WGwyM29KMkR2RjIxRncyU1dDYjNxTHgrWXVac3o4WGlrWjRSWTF1cUZDL2xm?= =?utf-8?B?NHNmU29ILzBON2R0R0Y2M25jNjBMVUsxeDYyd0ZsL2RtYzhkYVFYU25pTHZh?= =?utf-8?B?MXRxVk12RUtRZEpzNytaVmFOaVpFZFEvRW8rcHM0UjZYeHZ2eDRNcGhtbldz?= =?utf-8?B?NTA2VGJRVjVZVFluMkl0ZUE0Z2VVUDloOVpvQ2ZCZ2pwSGd6NDRhTi9NNHl5?= =?utf-8?B?cEFTdW5UZWN6amNHOFdGVWtuQnB3VmtzOExuUEhDZFdvbzV6VXd2b1M5WDZ6?= =?utf-8?B?QVRjR3kzMHRaditRbFVaSEZGWTIxR3VWUk1MeXVmblVGejdoS3NiYzlzQmlS?= =?utf-8?B?NVBNOFkrQ2ZDZC91OGMvbGFLNFBRVmxKY3BZejJJWEpIeDRTbWd1ZFpCZEs2?= =?utf-8?B?dTF6dkloVFpGK2ZVd0FuV3k3NmQ1OWFwaDFkQkM4aThscVV2NzZRY0RCOG9z?= =?utf-8?B?NDkzK1V4K3RkNXUwR0trR2xvNlhJWDBLY1JFZjhrdnFaQXMraWRDRllMc2RM?= =?utf-8?B?c2VLU3kvR3BqZ1dUajdxSk9JQmlLbFZ5dTNtOFJMbDhtNi90S1FLMXlTSy80?= =?utf-8?B?YVVQalNqd1g2UDRPejZKZVhNZ0NzWVBRTEI1ditwNEgyd3FvTC9yYnRhZVVD?= =?utf-8?B?Z214bmd4YjluNWFqZXc0c3JtWVRreWZOSHQxbWpiUWVzVng2OHM1Zm9LOU5x?= =?utf-8?B?YkFxbE5ROW1pTlJQbk9QTHJXb29QUDJyRkdjL1M3UFd4WHhlaHc1WWdIeW9z?= =?utf-8?B?NkVBanprQVFVVEhWTDUvc3kwdUxFcDNkaWhjSTVzOStpRDJHcXphYU1ZNEVh?= =?utf-8?B?dG5KRGJINTlndnl6ZHY5eUEyVUlxK0dwTTBuN3k3Njl0alJLSUV0TkdXS1la?= =?utf-8?B?SGlydEZzQmRDWkxtUGtIMDVwZ0dxSFRta25uQ0ZrNlJ1RzI2OWNRNndTbzg2?= =?utf-8?B?NENYOWZDT2NlSERDV3Z1QWlVQVVHYWdFRmQ3bkJ1a3BBUFpZZC82cjlvcjF4?= =?utf-8?B?QkREL1AvSlBydzBBNVlmR2FoaFpNWFZuaVBRQ0NZMllkSmtJMEdZd0ZmTzZz?= =?utf-8?B?L2N2Qm8wT2VyWHZBR3ZIUjhKcDVwM3A3SnpWNVhwdWI1K24raVZzcEVoK3pB?= =?utf-8?B?MGtVY3NnMXRQaXBMemNPV2l0MjJzL0ZJN0g1OUhNeE5QUVUyUUw3YmZYVi9L?= =?utf-8?B?TEUvZGU5Z1A0V0FxWW5MaEFYelR1WEV2U0lxdEY0bFBqNjk5bElOcS9VRkVi?= =?utf-8?B?WHp3MWpmaGFXYlRrNWo5aFloQ3M3K3M5dTF3c3EvUGY0ZlZOMk50WDMwRmZN?= =?utf-8?Q?on2ZjRnGGwFWYC7gxvcshlH1J?= Content-ID: <1E4A305856DC164AB4113C37DC897ED6@apcprd03.prod.outlook.com> MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: TYZPR03MB6624.apcprd03.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 42c77c68-45be-4d10-30d4-08dbcef489fe X-MS-Exchange-CrossTenant-originalarrivaltime: 17 Oct 2023 09:36:28.5299 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: a7687ede-7a6b-4ef6-bace-642f677fbe31 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: 0H9FbjPKLbdqkjpoEbqpvr0CvA7WWjkfM+jj3L8wAR181Lli5C1M1nWhQpn1laY6XgCa5V1eZo3OoOT6ue90yA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: TYZPR03MB7637 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231017_023714_708080_B9300AE5 X-CRM114-Status: GOOD ( 18.15 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi, Hsiao-chien: On Mon, 2023-10-16 at 18:40 +0800, Hsiao Chien Sung wrote: > Padding is a new display module on MT8188, it provides ability > to add pixels to width and height of a layer with specified colors. > > Due to hardware design, Mixer in VDOSYS1 requires width of a layer > to be 2-pixel-align, or 4-pixel-align when ETHDR is enabled, > we need Padding to deal with odd width. Reviewed-by: CK Hu > > Signed-off-by: Hsiao Chien Sung > --- > drivers/gpu/drm/mediatek/Makefile | 3 +- > drivers/gpu/drm/mediatek/mtk_disp_drv.h | 4 + > drivers/gpu/drm/mediatek/mtk_drm_drv.c | 1 + > drivers/gpu/drm/mediatek/mtk_drm_drv.h | 2 +- > drivers/gpu/drm/mediatek/mtk_padding.c | 160 > ++++++++++++++++++++++++ > 5 files changed, 168 insertions(+), 2 deletions(-) > create mode 100644 drivers/gpu/drm/mediatek/mtk_padding.c > > diff --git a/drivers/gpu/drm/mediatek/Makefile > b/drivers/gpu/drm/mediatek/Makefile > index d4d193f60271..5e4436403b8d 100644 > --- a/drivers/gpu/drm/mediatek/Makefile > +++ b/drivers/gpu/drm/mediatek/Makefile > @@ -16,7 +16,8 @@ mediatek-drm-y := mtk_disp_aal.o \ > mtk_dsi.o \ > mtk_dpi.o \ > mtk_ethdr.o \ > - mtk_mdp_rdma.o > + mtk_mdp_rdma.o \ > + mtk_padding.o > > obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o > > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h > b/drivers/gpu/drm/mediatek/mtk_disp_drv.h > index bf06ccb65652..e2b602037ac3 100644 > --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h > +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h > @@ -159,4 +159,8 @@ void mtk_mdp_rdma_config(struct device *dev, > struct mtk_mdp_rdma_cfg *cfg, > const u32 *mtk_mdp_rdma_get_formats(struct device *dev); > size_t mtk_mdp_rdma_get_num_formats(struct device *dev); > > +int mtk_padding_clk_enable(struct device *dev); > +void mtk_padding_clk_disable(struct device *dev); > +void mtk_padding_start(struct device *dev); > +void mtk_padding_stop(struct device *dev); > #endif > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c > b/drivers/gpu/drm/mediatek/mtk_drm_drv.c > index cdce165c092e..62e6e9785443 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c > +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c > @@ -1025,6 +1025,7 @@ static struct platform_driver * const > mtk_drm_drivers[] = { > &mtk_dsi_driver, > &mtk_ethdr_driver, > &mtk_mdp_rdma_driver, > + &mtk_padding_driver, > }; > > static int __init mtk_drm_init(void) > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h > b/drivers/gpu/drm/mediatek/mtk_drm_drv.h > index 8dca68ea1b94..d2efd715699f 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h > +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h > @@ -72,5 +72,5 @@ extern struct platform_driver mtk_dpi_driver; > extern struct platform_driver mtk_dsi_driver; > extern struct platform_driver mtk_ethdr_driver; > extern struct platform_driver mtk_mdp_rdma_driver; > - > +extern struct platform_driver mtk_padding_driver; > #endif /* MTK_DRM_DRV_H */ > diff --git a/drivers/gpu/drm/mediatek/mtk_padding.c > b/drivers/gpu/drm/mediatek/mtk_padding.c > new file mode 100644 > index 000000000000..fa2e7fc9c7bd > --- /dev/null > +++ b/drivers/gpu/drm/mediatek/mtk_padding.c > @@ -0,0 +1,160 @@ > +// SPDX-License-Identifier: GPL-2.0-only > +/* > + * Copyright (c) 2023 MediaTek Inc. > + */ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +#include "mtk_disp_drv.h" > +#include "mtk_drm_crtc.h" > +#include "mtk_drm_ddp_comp.h" > + > +#define PADDING_CONTROL_REG 0x00 > +#define PADDING_BYPASS BIT(0) > +#define PADDING_ENABLE BIT(1) > +#define PADDING_PIC_SIZE_REG 0x04 > +#define PADDING_H_REG 0x08 /* horizontal */ > +#define PADDING_V_REG 0x0c /* vertical */ > +#define PADDING_COLOR_REG 0x10 > + > +/** > + * struct mtk_padding - basic information of Padding > + * @clk: Clock of the module > + * @reg: Virtual address of the Padding for CPU to access > + * @cmdq_reg: CMDQ setting of the Padding > + * > + * Every Padding should have different clock source, register base, > and > + * CMDQ settings, we stored these differences all together. > + */ > +struct mtk_padding { > + struct clk *clk; > + void __iomem *reg; > + struct cmdq_client_reg cmdq_reg; > +}; > + > +int mtk_padding_clk_enable(struct device *dev) > +{ > + struct mtk_padding *padding = dev_get_drvdata(dev); > + > + return clk_prepare_enable(padding->clk); > +} > + > +void mtk_padding_clk_disable(struct device *dev) > +{ > + struct mtk_padding *padding = dev_get_drvdata(dev); > + > + clk_disable_unprepare(padding->clk); > +} > + > +void mtk_padding_start(struct device *dev) > +{ > + struct mtk_padding *padding = dev_get_drvdata(dev); > + > + writel(PADDING_ENABLE | PADDING_BYPASS, > + padding->reg + PADDING_CONTROL_REG); > + > + /* > + * notice that even the padding is in bypass mode, > + * all the settings must be cleared to 0 or > + * undefined behaviors could happen > + */ > + writel(0, padding->reg + PADDING_PIC_SIZE_REG); > + writel(0, padding->reg + PADDING_H_REG); > + writel(0, padding->reg + PADDING_V_REG); > + writel(0, padding->reg + PADDING_COLOR_REG); > +} > + > +void mtk_padding_stop(struct device *dev) > +{ > + struct mtk_padding *padding = dev_get_drvdata(dev); > + > + writel(0, padding->reg + PADDING_CONTROL_REG); > +} > + > +static int mtk_padding_bind(struct device *dev, struct device > *master, void *data) > +{ > + return 0; > +} > + > +static void mtk_padding_unbind(struct device *dev, struct device > *master, void *data) > +{ > +} > + > +static const struct component_ops mtk_padding_component_ops = { > + .bind = mtk_padding_bind, > + .unbind = mtk_padding_unbind, > +}; > + > +static int mtk_padding_probe(struct platform_device *pdev) > +{ > + struct device *dev = &pdev->dev; > + struct mtk_padding *priv; > + struct resource *res; > + int ret; > + > + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); > + if (!priv) > + return -ENOMEM; > + > + priv->clk = devm_clk_get(dev, NULL); > + if (IS_ERR(priv->clk)) { > + dev_err(dev, "failed to get clk\n"); > + return PTR_ERR(priv->clk); > + } > + > + priv->reg = devm_platform_get_and_ioremap_resource(pdev, 0, > &res); > + if (IS_ERR(priv->reg)) { > + dev_err(dev, "failed to do ioremap\n"); > + return PTR_ERR(priv->reg); > + } > + > +#if IS_REACHABLE(CONFIG_MTK_CMDQ) > + ret = cmdq_dev_get_client_reg(dev, &priv->cmdq_reg, 0); > + if (ret) { > + dev_err(dev, "failed to get gce client reg\n"); > + return ret; > + } > +#endif > + > + platform_set_drvdata(pdev, priv); > + > + ret = devm_pm_runtime_enable(dev); > + if (ret) > + return ret; > + > + ret = component_add(dev, &mtk_padding_component_ops); > + if (ret) { > + pm_runtime_disable(dev); > + return dev_err_probe(dev, ret, "failed to add > component\n"); > + } > + > + return 0; > +} > + > +static int mtk_padding_remove(struct platform_device *pdev) > +{ > + component_del(&pdev->dev, &mtk_padding_component_ops); > + return 0; > +} > + > +static const struct of_device_id mtk_padding_driver_dt_match[] = { > + { .compatible = "mediatek,mt8188-padding" }, > + { /* sentinel */ } > +}; > +MODULE_DEVICE_TABLE(of, mtk_padding_driver_dt_match); > + > +struct platform_driver mtk_padding_driver = { > + .probe = mtk_padding_probe, > + .remove = mtk_padding_remove, > + .driver = { > + .name = "mediatek-padding", > + .owner = THIS_MODULE, > + .of_match_table = mtk_padding_driver_dt_match, > + }, > +}; _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel