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Sat, 18 Jan 2025 02:07:38 -0800 (PST) Received: from jernej-laptop.localnet ([188.159.248.16]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ab384d2d3dcsm308908466b.81.2025.01.18.02.07.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 Jan 2025 02:07:37 -0800 (PST) From: Jernej =?UTF-8?B?xaBrcmFiZWM=?= To: Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Samuel Holland , Andre Przywara Cc: linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org Subject: Re: [PATCH 1/7] pinctrl: sunxi: refactor pinctrl variants into flags Date: Sat, 18 Jan 2025 11:07:36 +0100 Message-ID: <1881692.atdPhlSkOF@jernej-laptop> In-Reply-To: <20241111005750.13071-2-andre.przywara@arm.com> References: <20241111005750.13071-1-andre.przywara@arm.com> <20241111005750.13071-2-andre.przywara@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250118_020740_424664_D9F17774 X-CRM114-Status: GOOD ( 18.22 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Dne ponedeljek, 11. november 2024 ob 01:57:44 Srednjeevropski standardni = =C4=8Das je Andre Przywara napisal(a): > For some Allwinner SoCs we have one pinctrl driver caring for multiple > very similar chips, and are tagging certain pins with a variant bitmask. > The Allwinner D1 introduced a slightly extended register layout, and we > were abusing this variant mask to convey this bit of information into > the common code part. > Now there will be more pinctrl device properties to consider (has PortF > voltage switch, for instance), so shoehorning this into the variant > bitmask will not fly anymore. >=20 > Refactor the "variant" field into a more generic "flags" field. It turns > out that we don't need the variant bits to be unique across all SoCs, > but only among those SoCs that share one driver (table), of which there > are at most three variants at the moment. So the actual variant field can > be limited to say 8 bits, and the other bits in the flag register can be > re-purposed to hold other information, like this extended register > layout. > As a side effect we can move the variant definition into the per-SoC > pinctrl driver file, which makes it more obvious that this is just a > private definition, only relevant for this particular table. > This also changes the artificial sun20i-d1 "variant" into the actual > flag bit that we are after. >=20 > Signed-off-by: Andre Przywara That looks pretty neat cleanup. Reviewed-by: Jernej Skrabec Best regards, Jernej