Re: [PATCH 0/3] clk: meson: add support for PCIE PLL

[Neil Armstrong <narmstrong@baylibre.com>]

On 19/03/2019 11:01, Jerome Brunet wrote:
> On Thu, 2019-03-07 at 15:14 +0100, Neil Armstrong wrote:
>> The Amlogic G12A SoCs embeds a dedicated PLL to feed the USB3+PCIE
>> Combo PHY. This PLL needs a very specific and strict register sequence
>> in order to correcly enable it and deliver the 100MHz reference clock
>> to the Analog PHY.
>>
>> After lot of trials and errors, and since this PLL will ever feed 100MHz
>> with a static configuration, it is simpler to setup a dedicated ops
>> structure with a custom _enable() op applying the init register sequence.
>>
>> The rate calculation ops are kept in order to keep the nominal read
>> ops as-in, but set_rate is removed.
>>
>> With this setup, the PLL can be enabled and disable safely and always have
>> the recommended PLL setup to feed the USB3+PCIE Combo PHY.
>>
>> Neil Armstrong (3):
>>   clk: meson-pll: add reduced specific clk_ops for G12A PCIe PLL
>>   dt-bindings: clk: g12a-clkc: add PCIE PLL clock ID
>>   clk: meson-g12a: add PCIE PLL clocks
>>
>>  drivers/clk/meson/clk-pll.c           |  26 ++++++
>>  drivers/clk/meson/clk-pll.h           |   1 +
>>  drivers/clk/meson/g12a.c              | 118 ++++++++++++++++++++++++++
>>  drivers/clk/meson/g12a.h              |   5 +-
>>  include/dt-bindings/clock/g12a-clkc.h |   1 +
>>  5 files changed, 150 insertions(+), 1 deletion(-)
> 
> Well this PLL is indeed a nasty one ;)
> 
> Acked-by: Jerome Brunet <jbrunet@baylibre.com>
> 

Applied patch 2 on next/headers, patches 1 & 3 on next/drivers

Neil

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