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[68.101.123.102]) by smtp.gmail.com with ESMTPSA id h14sm242352pgj.8.2019.06.05.19.51.53 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 05 Jun 2019 19:51:54 -0700 (PDT) Subject: Re: [PATCH V2 1/2] DT: mailbox: add binding doc for the ARM SMC mailbox To: Andre Przywara , Sudeep Holla References: <20190603083005.4304-1-peng.fan@nxp.com> <20190603083005.4304-2-peng.fan@nxp.com> <20190603165651.GA12196@e107155-lin> <20190603181856.34996aaa@donnerap.cambridge.arm.com> From: Florian Fainelli Openpgp: preference=signencrypt Message-ID: <19931084-8b12-c510-8856-5cc869e4f9ff@gmail.com> Date: Wed, 5 Jun 2019 19:51:52 -0700 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:60.0) Gecko/20100101 Thunderbird/60.7.0 MIME-Version: 1.0 In-Reply-To: <20190603181856.34996aaa@donnerap.cambridge.arm.com> Content-Language: en-US X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190605_195157_679103_951E568C X-CRM114-Status: GOOD ( 20.03 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.rutland@arm.com, devicetree@vger.kernel.org, peng.fan@nxp.com, festevam@gmail.com, jassisinghbrar@gmail.com, linux-kernel@vger.kernel.org, robh+dt@kernel.org, linux-imx@nxp.com, kernel@pengutronix.de, van.freenix@gmail.com, shawnguo@kernel.org, linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 6/3/2019 10:18 AM, Andre Przywara wrote: > On Mon, 3 Jun 2019 17:56:51 +0100 > Sudeep Holla wrote: > > Hi, > >> On Mon, Jun 03, 2019 at 09:22:16AM -0700, Florian Fainelli wrote: >>> On 6/3/19 1:30 AM, peng.fan@nxp.com wrote: >>>> From: Peng Fan >>>> >>>> The ARM SMC mailbox binding describes a firmware interface to trigger >>>> actions in software layers running in the EL2 or EL3 exception levels. >>>> The term "ARM" here relates to the SMC instruction as part of the ARM >>>> instruction set, not as a standard endorsed by ARM Ltd. >>>> >>>> Signed-off-by: Peng Fan >>>> --- >>>> >>>> V2: >>>> Introduce interrupts as a property. >>>> >>>> V1: >>>> arm,func-ids is still kept as an optional property, because there is no >>>> defined SMC funciton id passed from SCMI. So in my test, I still use >>>> arm,func-ids for ARM SIP service. >>>> >>>> .../devicetree/bindings/mailbox/arm-smc.txt | 101 +++++++++++++++++++++ >>>> 1 file changed, 101 insertions(+) >>>> create mode 100644 Documentation/devicetree/bindings/mailbox/arm-smc.txt >>>> >>>> diff --git a/Documentation/devicetree/bindings/mailbox/arm-smc.txt b/Documentation/devicetree/bindings/mailbox/arm-smc.txt >>>> new file mode 100644 >>>> index 000000000000..401887118c09 >>>> --- /dev/null >>>> +++ b/Documentation/devicetree/bindings/mailbox/arm-smc.txt >>>> @@ -0,0 +1,101 @@ >> >> [...] >> >>>> +Optional properties: >>>> +- arm,func-ids An array of 32-bit values specifying the function >>>> + IDs used by each mailbox channel. Those function IDs >>>> + follow the ARM SMC calling convention standard [1]. >>>> + There is one identifier per channel and the number >>>> + of supported channels is determined by the length >>>> + of this array. >>>> +- interrupts SPI interrupts may be listed for notification, >>>> + each channel should use a dedicated interrupt >>>> + line. >>> >>> I would not go about defining a specific kind of interrupt, since SPI is >>> a GIC terminology, this firmware interface could be used in premise with >>> any parent interrupt controller, for which the concept of a SPI/PPI/SGI >>> may not be relevant. >>> >> >> While I agree the binding document may not contain specifics, I still >> don't see how to use SGI with this. Also note it's generally reserved >> for OS future use(IPC) and using this for other than IPC may be bit >> challenging IMO. It opens up lots of questions. > > Well, a PPI might be possible to use, although it's somewhat dodgy to hijack the GIC's (re-)distributor from EL3 to write to GICD_ISPENDR. Need to ask Marc about his feelings towards this. But it's definitely possible from a hypervisor to inject arbitrary interrupts into a guest. > > But more importantly: is there any actual reason this needs to be a GIC interrupt? If I understand the code correctly, this could just be any interrupt, including one of an interrupt combiner or a GPIO chip. So why not just use the standard wording of: "exactly one interrupt specifier for each channel"? That was my point, I am not stuck on using an SGI, or PPI, or anything (even if that's what we have been using at the moment), any interrupt would/should do here so the wording should be exactly as you indicated. -- Florian _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel