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Sat, 08 Mar 2025 23:00:22 -0800 (PST) Received: from jernej-laptop.localnet ([188.159.248.16]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ac299a025c7sm14713966b.51.2025.03.08.23.00.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 08 Mar 2025 23:00:22 -0800 (PST) From: Jernej =?UTF-8?B?xaBrcmFiZWM=?= To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Samuel Holland , Andre Przywara Cc: Philipp Zabel , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org Subject: Re: [PATCH v4 13/14] clk: sunxi-ng: a523: add reset lines Date: Sun, 09 Mar 2025 08:00:20 +0100 Message-ID: <1994155.PYKUYFuaPT@jernej-laptop> In-Reply-To: <20250307002628.10684-14-andre.przywara@arm.com> References: <20250307002628.10684-1-andre.przywara@arm.com> <20250307002628.10684-14-andre.przywara@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250308_230024_496868_02C97245 X-CRM114-Status: GOOD ( 11.64 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Dne petek, 7. marec 2025 ob 01:26:27 Srednjeevropski standardni =C4=8Das je= Andre Przywara napisal(a): > Allwinner SoCs do not contain a separate reset controller, instead the > reset lines for the various devices are integrated into the "BGR" (Bus > Gate / Reset) registers, for each device group: one for all UARTs, one > for all SPI interfaces, and so on. > The Allwinner CCU driver also doubles as a reset provider, and since the > reset lines are indeed just single bits in those BGR register, we can > represent them easily in an array of structs, just containing the > register offset and the bit number. >=20 > Add the location of the reset bits for all devices in the A523/T527 > SoCs, using the existing sunxi CCU infrastructure. >=20 > Signed-off-by: Andre Przywara Reviewed-by: Jernej Skrabec Best regards, Jernej