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Thu, 16 Jan 2020 16:11:51 -0000 (UTC) Received: by smtp.codeaurora.org (Postfix, from userid 1001) id 0A1DAC447A2; Thu, 16 Jan 2020 16:11:50 +0000 (UTC) Received: from mail.codeaurora.org (localhost.localdomain [127.0.0.1]) (using TLSv1 with cipher ECDHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) (Authenticated sender: saiprakash.ranjan) by smtp.codeaurora.org (Postfix) with ESMTPSA id 4346EC43383; Thu, 16 Jan 2020 16:11:50 +0000 (UTC) MIME-Version: 1.0 Date: Thu, 16 Jan 2020 21:41:50 +0530 From: Sai Prakash Ranjan To: Will Deacon Subject: Re: [PATCH] arm64: Add KRYO{3,4}XX CPU cores to spectre-v2 safe list In-Reply-To: <20200116153235.GA18909@willie-the-truck> References: <20200116141912.15465-1-saiprakash.ranjan@codeaurora.org> <20200116153235.GA18909@willie-the-truck> Message-ID: <1a3f9557fa52ce2528630434e9a49d98@codeaurora.org> X-Sender: saiprakash.ranjan@codeaurora.org User-Agent: Roundcube Webmail/1.3.9 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200116_081158_606871_1D7140C8 X-CRM114-Status: GOOD ( 16.58 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , Marc Zyngier , jhugo@codeaurora.org, Catalin Marinas , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, Douglas Anderson , Matthias Kaehlcke , Bjorn Andersson , Andre Przywara , James Morse , Stephen Boyd , linux-arm-kernel@lists.infradead.org Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Will, On 2020-01-16 21:02, Will Deacon wrote: > [+Jeffrey] > > On Thu, Jan 16, 2020 at 07:49:12PM +0530, Sai Prakash Ranjan wrote: >> KRYO3XX silver CPU cores and KRYO4XX silver, gold CPU cores >> are not affected by Spectre variant 2. Add them to spectre_v2 >> safe list to correct ARM_SMCCC_ARCH_WORKAROUND_1 warning and >> vulnerability sysfs value. >> >> Signed-off-by: Sai Prakash Ranjan >> --- >> arch/arm64/include/asm/cputype.h | 6 ++++++ >> arch/arm64/kernel/cpu_errata.c | 3 +++ >> 2 files changed, 9 insertions(+) >> >> diff --git a/arch/arm64/include/asm/cputype.h >> b/arch/arm64/include/asm/cputype.h >> index aca07c2f6e6e..7219cddeba66 100644 >> --- a/arch/arm64/include/asm/cputype.h >> +++ b/arch/arm64/include/asm/cputype.h >> @@ -85,6 +85,9 @@ >> #define QCOM_CPU_PART_FALKOR_V1 0x800 >> #define QCOM_CPU_PART_FALKOR 0xC00 >> #define QCOM_CPU_PART_KRYO 0x200 >> +#define QCOM_CPU_PART_KRYO_3XX_SILVER 0x803 >> +#define QCOM_CPU_PART_KRYO_4XX_GOLD 0x804 >> +#define QCOM_CPU_PART_KRYO_4XX_SILVER 0x805 > > Jeffrey is the only person I know who understands the CPU naming here, > so > I've added him in case this needs either renaming or extending to cover > other CPUs. I wouldn't be at all surprised if we need a function call > rather than a bunch of table entries... > > That said, the internet claims that KRYO4XX gold is based on > Cortex-A76, > and so CSV2 should be set... > Yes the internet claims are true and CSV2 is set. SANITY check logs in here show ID_PFR0_EL1 - https://lore.kernel.org/patchwork/patch/1138457/ Thanks, Sai -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel