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Tue, 10 Nov 2026 07:31:56 -0800 (PST) Received: from [192.168.1.3] ([37.18.141.193]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4984e26f8e3sm4917105f8f.1.2026.11.10.07.31.54 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 10 Nov 2026 07:31:55 -0800 (PST) Message-ID: <1b528cd9-eac0-43b3-8166-db9f78c9f044@linaro.org> Date: Tue, 10 Nov 2026 15:31:54 +0000 X-Archived-By: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 11/23] coresight: trbe: Assign the perf handle in enable and disable To: Leo Yan Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, coresight@lists.linaro.org, Suzuki K Poulose , Mike Leach , Alexander Shishkin , Anshuman Khandual , Tamas Petz , Tamas Zsoldos , Suyash Mahar , Amir Ayupov References: <20261016-trbe_enable_disable_irq_handle_refactor-v2-0-3f57cf3199b1@arm.com> <20261016-trbe_enable_disable_irq_handle_refactor-v2-11-3f57cf3199b1@arm.com> Content-Language: en-US From: James Clark In-Reply-To: <20261016-trbe_enable_disable_irq_handle_refactor-v2-11-3f57cf3199b1@arm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20261110_073158_250128_BC5E7AB3 X-CRM114-Status: GOOD ( 22.46 ) X-Spam-Score: -2.1 (--) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" X-Spam-Status: No, score=-17.4 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 On 16/10/2026 17:55, Leo Yan wrote: > etm-perf owns the perf output handle embedded in its per-CPU etm_ctxt and > passes it to TRBE through arm_trbe_enable(). TRBE binds that handle after > successful sink enable and unbinds it in arm_trbe_disable(). The handle > object remains valid throughout this interval, even if the current AUX > transaction ends or a new transaction begins. > > The inner enable helper currently publishes the handle, while truncation > and failed rollover clear it. Sink disable leaves the handle installed > after dropping the buffer association. These assignments track the AUX > transaction rather than the enabled sink session. > > Publish the handle only in arm_trbe_enable() after successful setup and > clear it in arm_trbe_disable() before dropping the buffer association. > Remove the assignments from the inner enable, overflow and truncation > paths so the handle association follows the enabled sink session. > > A valid handle object may have no active AUX transaction, so the IRQ > handler continues to check perf_get_aux() before accessing the > transaction's configuration. > > Signed-off-by: Leo Yan > --- > drivers/hwtracing/coresight/coresight-trbe.c | 20 +++++++------------- > 1 file changed, 7 insertions(+), 13 deletions(-) > > diff --git a/drivers/hwtracing/coresight/coresight-trbe.c b/drivers/hwtracing/coresight/coresight-trbe.c > index 4a041bbc6e970d72a7d735e15f7221037cb091d6..1f51c33de83638479436683fd96e31d69c3b860f 100644 > --- a/drivers/hwtracing/coresight/coresight-trbe.c > +++ b/drivers/hwtracing/coresight/coresight-trbe.c > @@ -303,11 +303,8 @@ static void trbe_report_wrap_event(struct perf_output_handle *handle) > > static void trbe_truncate_event(struct perf_output_handle *handle) > { > - struct trbe_buf *buf = etm_perf_sink_config(handle); > - > perf_aux_output_flag(handle, PERF_AUX_FLAG_TRUNCATED); > perf_aux_output_end(handle, 0); > - *this_cpu_ptr(buf->cpudata->drvdata->handle) = NULL; > } > > /* > @@ -1012,7 +1009,6 @@ static int __arm_trbe_enable(struct trbe_buf *buf, > if (ret) > goto err; > > - *this_cpu_ptr(buf->cpudata->drvdata->handle) = handle; > trbe_enable_hw(buf); > return 0; > err: > @@ -1042,6 +1038,7 @@ static int arm_trbe_enable(struct coresight_device *csdev, enum cs_mode mode, > return ret; > } > > + *this_cpu_ptr(drvdata->handle) = handle; > cpudata->buf = buf; > cpudata->mode = mode; > return 0; > @@ -1062,6 +1059,7 @@ static int arm_trbe_disable(struct coresight_device *csdev) > trbe_drain_and_disable_local(cpudata); > clr_trbe_status(); > > + *this_cpu_ptr(drvdata->handle) = NULL; > buf->cpudata = NULL; > cpudata->buf = NULL; > cpudata->mode = CS_MODE_DISABLED; > @@ -1102,16 +1100,12 @@ static int trbe_handle_overflow(struct perf_output_handle *handle) > trbe_report_wrap_event(handle); > perf_aux_output_end(handle, size); > event_data = perf_aux_output_begin(handle, event); > - if (!event_data) { > - /* > - * We are unable to restart the trace collection, > - * thus leave the TRBE disabled. The etm-perf driver > - * is able to detect this with a disconnected handle > - * (handle->event = NULL). > - */ > - *this_cpu_ptr(buf->cpudata->drvdata->handle) = NULL; > + /* > + * If trace collection cannot be restarted, leave TRBE disabled. > + * The etm-perf driver detects this through handle->event == NULL. > + */ > + if (!event_data) > return -EINVAL; > - } > > return __arm_trbe_enable(buf, handle); > } > Reviewed-by: James Clark