[PATCH 0/3] Adding brcmstb-hwspinlock support

[PATCH 0/3] Adding brcmstb-hwspinlock support

[Kamal Dasu]

This is standalone patch for the harware semaphore feature for
brcnstb SoCs. The initial patch was sent as part of different patch
set shown below. That was not accepted, however the hwspinlock feature
is geenric for all brcmstb SoCs.

Intial patch:
url:    https://github.com/intel-lab-lkp/linux/commits/Kamal-Dasu/dt-bindings-brcmstb-hwspinlock-support-for-hwspinlock/20250712-034624
base:   https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
patch link:    https://lore.kernel.org/r/20250711154221.928164-4-kamal.dasu%40broadcom.com
patch subject: [PATCH 2/4] hwspinlock: brcmstb hardware semaphore support

All the review comments and build warning have been fixed in the current version.

Kamal Dasu (3):
  dt-bindings: hwlock:  Adding brcmstb-hwspinlock support
  hwspinlock: brcmstb hardware semaphore support
  MAINTAINERS: adding entry for BRCMSTB HWSPINLOCK driver

 .../hwlock/brcm,brcmstb-hwspinlock.yaml       | 36 +++++++
 MAINTAINERS                                   |  8 ++
 drivers/hwspinlock/Kconfig                    |  9 ++
 drivers/hwspinlock/Makefile                   |  1 +
 drivers/hwspinlock/brcmstb_hwspinlock.c       | 98 +++++++++++++++++++
 5 files changed, 152 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/hwlock/brcm,brcmstb-hwspinlock.yaml
 create mode 100644 drivers/hwspinlock/brcmstb_hwspinlock.c

-- 
2.34.1

[PATCH 1/3] dt-bindings: hwlock: Adding brcmstb-hwspinlock support

[Kamal Dasu]

Adding brcmstb-hwspinlock bindings.

Signed-off-by: Kamal Dasu <kamal.dasu@broadcom.com>
---
 .../hwlock/brcm,brcmstb-hwspinlock.yaml       | 36 +++++++++++++++++++
 1 file changed, 36 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/hwlock/brcm,brcmstb-hwspinlock.yaml

diff --git a/Documentation/devicetree/bindings/hwlock/brcm,brcmstb-hwspinlock.yaml b/Documentation/devicetree/bindings/hwlock/brcm,brcmstb-hwspinlock.yaml
new file mode 100644
index 000000000000..f45399b4fe0b
--- /dev/null
+++ b/Documentation/devicetree/bindings/hwlock/brcm,brcmstb-hwspinlock.yaml
@@ -0,0 +1,36 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/hwlock/brcm,brcmstb-hwspinlock.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Broadcom settop Hardware Spinlock
+
+maintainers:
+  - Kamal Dasu <kamal.dasu@broadcom.com>
+
+properties:
+  compatible:
+    const: brcm,brcmstb-hwspinlock
+
+  "#hwlock-cells":
+    const: 1
+
+  reg:
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - "#hwlock-cells"
+
+additionalProperties: false
+
+examples:
+  - |
+    hwlock@8404038 {
+        compatible = "brcm,brcmstb-hwspinlock";
+        reg = <0x8404038 0x40>;
+        #hwlock-cells = <1>;
+    };
+
-- 
2.34.1

[PATCH 1/3] dt-bindings: hwlock: support for brcmstb-hwspinlock

[Kamal Dasu]

Adding brcmstb-hwspinlock bindings.

Signed-off-by: Kamal Dasu <kamal.dasu@broadcom.com>
---
 .../hwlock/brcm,brcmstb-hwspinlock.yaml       | 36 +++++++++++++++++++
 1 file changed, 36 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/hwlock/brcm,brcmstb-hwspinlock.yaml

diff --git a/Documentation/devicetree/bindings/hwlock/brcm,brcmstb-hwspinlock.yaml b/Documentation/devicetree/bindings/hwlock/brcm,brcmstb-hwspinlock.yaml
new file mode 100644
index 000000000000..f45399b4fe0b
--- /dev/null
+++ b/Documentation/devicetree/bindings/hwlock/brcm,brcmstb-hwspinlock.yaml
@@ -0,0 +1,36 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/hwlock/brcm,brcmstb-hwspinlock.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Broadcom settop Hardware Spinlock
+
+maintainers:
+  - Kamal Dasu <kamal.dasu@broadcom.com>
+
+properties:
+  compatible:
+    const: brcm,brcmstb-hwspinlock
+
+  "#hwlock-cells":
+    const: 1
+
+  reg:
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - "#hwlock-cells"
+
+additionalProperties: false
+
+examples:
+  - |
+    hwlock@8404038 {
+        compatible = "brcm,brcmstb-hwspinlock";
+        reg = <0x8404038 0x40>;
+        #hwlock-cells = <1>;
+    };
+
-- 
2.34.1

[PATCH 2/3] hwspinlock: brcmstb hardware semaphore support

[Kamal Dasu]

Added support for brmstb_hwspinlock driver that makes use of
the hwspinlock framework. Driver uses SUN_TOP_CTRL_SEMAPHORE_[1:15]
registers to implement the hardware semaphore. With this change
other brcmstb drivers can use hwspin_trylock() and hwspin_unlock()
apis and make use of this hwspinlock framework. Other driver dt nodes
just need to use a reference to the &hwspinlock and the lock id
they want to use.
e.g. hwlocks = <&hwspinlock0 0>;

Signed-off-by: Kamal Dasu <kamal.dasu@broadcom.com>
---
 drivers/hwspinlock/Kconfig              |  9 +++
 drivers/hwspinlock/Makefile             |  1 +
 drivers/hwspinlock/brcmstb_hwspinlock.c | 98 +++++++++++++++++++++++++
 3 files changed, 108 insertions(+)
 create mode 100644 drivers/hwspinlock/brcmstb_hwspinlock.c

diff --git a/drivers/hwspinlock/Kconfig b/drivers/hwspinlock/Kconfig
index 3874d15b0e9b..551afa8df2d0 100644
--- a/drivers/hwspinlock/Kconfig
+++ b/drivers/hwspinlock/Kconfig
@@ -63,4 +63,13 @@ config HSEM_U8500
 
 	  If unsure, say N.
 
+config HWSPINLOCK_BRCMSTB
+	tristate "Broadcom Setttop Hardware Semaphore functionality"
+	depends on ARCH_BRCMSTB || COMPILE_TEST
+	help
+	  Broadcom settop hwspinlock driver.
+	  Say y here to support the Broadcom Hardware Semaphore functionality, which
+	  provides a synchronisation mechanism on the SoC.
+
+	  If unsure, say N.
 endif # HWSPINLOCK
diff --git a/drivers/hwspinlock/Makefile b/drivers/hwspinlock/Makefile
index a0f16c9aaa82..4f5c05403209 100644
--- a/drivers/hwspinlock/Makefile
+++ b/drivers/hwspinlock/Makefile
@@ -10,3 +10,4 @@ obj-$(CONFIG_HWSPINLOCK_SPRD)		+= sprd_hwspinlock.o
 obj-$(CONFIG_HWSPINLOCK_STM32)		+= stm32_hwspinlock.o
 obj-$(CONFIG_HWSPINLOCK_SUN6I)		+= sun6i_hwspinlock.o
 obj-$(CONFIG_HSEM_U8500)		+= u8500_hsem.o
+obj-$(CONFIG_HWSPINLOCK_BRCMSTB)	+= brcmstb_hwspinlock.o
diff --git a/drivers/hwspinlock/brcmstb_hwspinlock.c b/drivers/hwspinlock/brcmstb_hwspinlock.c
new file mode 100644
index 000000000000..56206431a94c
--- /dev/null
+++ b/drivers/hwspinlock/brcmstb_hwspinlock.c
@@ -0,0 +1,98 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * brcmstb HWSEM driver
+ *
+ * Copyright (C) 2025 Broadcom
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/slab.h>
+#include <linux/spinlock.h>
+#include <linux/hwspinlock.h>
+#include <linux/platform_device.h>
+#include <linux/mod_devicetable.h>
+#include "hwspinlock_internal.h"
+
+#define BRCMSTB_MAX_SEMAPHORES		16
+#define RESET_SEMAPHORE			0
+
+#define HWSPINLOCK_VAL			'L'
+
+static int brcmstb_hwspinlock_trylock(struct hwspinlock *lock)
+{
+	void __iomem *lock_addr = (void __iomem *)lock->priv;
+
+	writel(HWSPINLOCK_VAL, lock_addr);
+
+	return (readl(lock_addr) == HWSPINLOCK_VAL);
+}
+
+static void brcmstb_hwspinlock_unlock(struct hwspinlock *lock)
+{
+	void __iomem *lock_addr = (void __iomem *)lock->priv;
+
+	/* release the lock by writing 0 to it */
+	writel(RESET_SEMAPHORE, lock_addr);
+}
+
+static void brcmstb_hwspinlock_relax(struct hwspinlock *lock)
+{
+	ndelay(50);
+}
+
+static const struct hwspinlock_ops brcmstb_hwspinlock_ops = {
+	.trylock	= brcmstb_hwspinlock_trylock,
+	.unlock		= brcmstb_hwspinlock_unlock,
+	.relax		= brcmstb_hwspinlock_relax,
+};
+
+static int brcmstb_hwspinlock_probe(struct platform_device *pdev)
+{
+	struct hwspinlock_device *bank;
+	struct hwspinlock *hwlock;
+	void __iomem *io_base;
+	int i, num_locks = BRCMSTB_MAX_SEMAPHORES;
+
+	io_base = devm_platform_ioremap_resource(pdev, 0);
+	if (IS_ERR(io_base)) {
+		dev_err(&pdev->dev, "semaphore iobase mapping error\n");
+		return PTR_ERR(io_base);
+	}
+
+	bank = devm_kzalloc(&pdev->dev, struct_size(bank, lock, num_locks),
+			    GFP_KERNEL);
+	if (!bank)
+		return -ENOMEM;
+
+	platform_set_drvdata(pdev, bank);
+
+	for (i = 0, hwlock = &bank->lock[0]; i < num_locks; i++, hwlock++)
+		hwlock->priv = (void __iomem *)(io_base + sizeof(u32) * i);
+
+	return devm_hwspin_lock_register(&pdev->dev, bank,
+					 &brcmstb_hwspinlock_ops,
+					 0, num_locks);
+}
+
+static const struct of_device_id brcmstb_hwspinlock_ids[] = {
+	{ .compatible = "brcm,brcmstb-hwspinlock", },
+	{ /* end */ },
+};
+MODULE_DEVICE_TABLE(of, brcmstb_hwspinlock_ids);
+
+static struct platform_driver brcmstb_hwspinlock_driver = {
+	.probe		= brcmstb_hwspinlock_probe,
+	.driver		= {
+		.name	= "brcmstb_hwspinlock",
+		.of_match_table = brcmstb_hwspinlock_ids,
+	},
+};
+
+module_platform_driver(brcmstb_hwspinlock_driver);
+
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("Hardware Spinlock driver for brcmstb");
+MODULE_AUTHOR("Kamal Dasu <kdasu.dasu@broadcom.com>");
-- 
2.34.1

[PATCH 3/3] MAINTAINERS: adding entry for BRCMSTB HWSPINLOCK driver

[Kamal Dasu]

Signed-off-by: Kamal Dasu <kamal.dasu@broadcom.com>
---
 MAINTAINERS | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index 97d958c945e4..21b78f468169 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -4972,6 +4972,14 @@ S:	Supported
 F:	Documentation/devicetree/bindings/gpio/brcm,brcmstb-gpio.yaml
 F:	drivers/gpio/gpio-brcmstb.c
 
+BROADCOM BRCMSTB HWSPINLOCK DRIVER
+M:	Kamal Dasu <kamal.dasu@broadcom.com>
+R:	Broadcom internal kernel review list <bcm-kernel-feedback-list@broadcom.com>
+L:	linux-remoteproc@vger.kernel.org
+S:	Supported
+F:	Documentation/devicetree/bindings/hwlock/brcm,brcmstb-hwspinlock.yaml
+F:	drivers/hwspinlock/brcmstb_hwspinlock.c
+
 BROADCOM BRCMSTB I2C DRIVER
 M:	Kamal Dasu <kamal.dasu@broadcom.com>
 R:	Broadcom internal kernel review list <bcm-kernel-feedback-list@broadcom.com>
-- 
2.34.1

Re: [PATCH 1/3] dt-bindings: hwlock: Adding brcmstb-hwspinlock support

[Conor Dooley]

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On Mon, Sep 29, 2025 at 04:06:24PM -0400, Kamal Dasu wrote:
> Adding brcmstb-hwspinlock bindings.
> 
> Signed-off-by: Kamal Dasu <kamal.dasu@broadcom.com>
> ---
>  .../hwlock/brcm,brcmstb-hwspinlock.yaml       | 36 +++++++++++++++++++
>  1 file changed, 36 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/hwlock/brcm,brcmstb-hwspinlock.yaml
> 
> diff --git a/Documentation/devicetree/bindings/hwlock/brcm,brcmstb-hwspinlock.yaml b/Documentation/devicetree/bindings/hwlock/brcm,brcmstb-hwspinlock.yaml
> new file mode 100644
> index 000000000000..f45399b4fe0b
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/hwlock/brcm,brcmstb-hwspinlock.yaml
> @@ -0,0 +1,36 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/hwlock/brcm,brcmstb-hwspinlock.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Broadcom settop Hardware Spinlock
> +
> +maintainers:
> +  - Kamal Dasu <kamal.dasu@broadcom.com>
> +
> +properties:
> +  compatible:
> +    const: brcm,brcmstb-hwspinlock

Is "brcmstb" actually the name of a single platform?
Looking at the "brcmstb" pci binding, it looks like there's a whole load
of different devices there and none use "brcmstb":
          - brcm,bcm2711-pcie # The Raspberry Pi 4
          - brcm,bcm2712-pcie # Raspberry Pi 5
          - brcm,bcm4908-pcie
          - brcm,bcm7211-pcie # Broadcom STB version of RPi4
          - brcm,bcm7216-pcie # Broadcom 7216 Arm
          - brcm,bcm7278-pcie # Broadcom 7278 Arm
          - brcm,bcm7425-pcie # Broadcom 7425 MIPs
          - brcm,bcm7435-pcie # Broadcom 7435 MIPs
          - brcm,bcm7445-pcie # Broadcom 7445 Arm
          - brcm,bcm7712-pcie # Broadcom STB sibling of Rpi 5

If "stb" means "set top box", it sounds like a catchall for disparate
devices, which isn't permitted.

> +
> +  "#hwlock-cells":
> +    const: 1
> +
> +  reg:
> +    maxItems: 1
> +
> +required:
> +  - compatible
> +  - reg
> +  - "#hwlock-cells"
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    hwlock@8404038 {
> +        compatible = "brcm,brcmstb-hwspinlock";
> +        reg = <0x8404038 0x40>;
> +        #hwlock-cells = <1>;
> +    };
> +
> -- 
> 2.34.1
> 

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Re: [PATCH 1/3] dt-bindings: hwlock: support for brcmstb-hwspinlock

[Conor Dooley]

[-- Attachment #1: Type: text/plain, Size: 1573 bytes --]

On Mon, Sep 29, 2025 at 04:06:25PM -0400, Kamal Dasu wrote:
> Adding brcmstb-hwspinlock bindings.
> 
> Signed-off-by: Kamal Dasu <kamal.dasu@broadcom.com>

You have two 1/3 patches in this series.

> ---
>  .../hwlock/brcm,brcmstb-hwspinlock.yaml       | 36 +++++++++++++++++++
>  1 file changed, 36 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/hwlock/brcm,brcmstb-hwspinlock.yaml
> 
> diff --git a/Documentation/devicetree/bindings/hwlock/brcm,brcmstb-hwspinlock.yaml b/Documentation/devicetree/bindings/hwlock/brcm,brcmstb-hwspinlock.yaml
> new file mode 100644
> index 000000000000..f45399b4fe0b
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/hwlock/brcm,brcmstb-hwspinlock.yaml
> @@ -0,0 +1,36 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/hwlock/brcm,brcmstb-hwspinlock.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Broadcom settop Hardware Spinlock
> +
> +maintainers:
> +  - Kamal Dasu <kamal.dasu@broadcom.com>
> +
> +properties:
> +  compatible:
> +    const: brcm,brcmstb-hwspinlock
> +
> +  "#hwlock-cells":
> +    const: 1
> +
> +  reg:
> +    maxItems: 1
> +
> +required:
> +  - compatible
> +  - reg
> +  - "#hwlock-cells"
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    hwlock@8404038 {
> +        compatible = "brcm,brcmstb-hwspinlock";
> +        reg = <0x8404038 0x40>;
> +        #hwlock-cells = <1>;
> +    };
> +
> -- 
> 2.34.1
> 

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Re: [PATCH 1/3] dt-bindings: hwlock: Adding brcmstb-hwspinlock support

[Florian Fainelli]

On 9/30/25 12:03, Conor Dooley wrote:
> On Mon, Sep 29, 2025 at 04:06:24PM -0400, Kamal Dasu wrote:
>> Adding brcmstb-hwspinlock bindings.
>>
>> Signed-off-by: Kamal Dasu <kamal.dasu@broadcom.com>
>> ---
>>   .../hwlock/brcm,brcmstb-hwspinlock.yaml       | 36 +++++++++++++++++++
>>   1 file changed, 36 insertions(+)
>>   create mode 100644 Documentation/devicetree/bindings/hwlock/brcm,brcmstb-hwspinlock.yaml
>>
>> diff --git a/Documentation/devicetree/bindings/hwlock/brcm,brcmstb-hwspinlock.yaml b/Documentation/devicetree/bindings/hwlock/brcm,brcmstb-hwspinlock.yaml
>> new file mode 100644
>> index 000000000000..f45399b4fe0b
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/hwlock/brcm,brcmstb-hwspinlock.yaml
>> @@ -0,0 +1,36 @@
>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/hwlock/brcm,brcmstb-hwspinlock.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Broadcom settop Hardware Spinlock
>> +
>> +maintainers:
>> +  - Kamal Dasu <kamal.dasu@broadcom.com>
>> +
>> +properties:
>> +  compatible:
>> +    const: brcm,brcmstb-hwspinlock
> 
> Is "brcmstb" actually the name of a single platform?
> Looking at the "brcmstb" pci binding, it looks like there's a whole load
> of different devices there and none use "brcmstb":
>            - brcm,bcm2711-pcie # The Raspberry Pi 4
>            - brcm,bcm2712-pcie # Raspberry Pi 5
>            - brcm,bcm4908-pcie
>            - brcm,bcm7211-pcie # Broadcom STB version of RPi4
>            - brcm,bcm7216-pcie # Broadcom 7216 Arm
>            - brcm,bcm7278-pcie # Broadcom 7278 Arm
>            - brcm,bcm7425-pcie # Broadcom 7425 MIPs
>            - brcm,bcm7435-pcie # Broadcom 7435 MIPs
>            - brcm,bcm7445-pcie # Broadcom 7445 Arm
>            - brcm,bcm7712-pcie # Broadcom STB sibling of Rpi 5
> 
> If "stb" means "set top box", it sounds like a catchall for disparate
> devices, which isn't permitted.

Unlike PCIe, the HW spinlock hardware has been stable across all Set-top 
box chips ever since it was added, which is why the catch all is IMHO 
adequate here.
-- 
Florian

Re: [PATCH 1/3] dt-bindings: hwlock: Adding brcmstb-hwspinlock support

[Conor Dooley]

[-- Attachment #1: Type: text/plain, Size: 2609 bytes --]

On Tue, Sep 30, 2025 at 12:09:01PM -0700, Florian Fainelli wrote:
> On 9/30/25 12:03, Conor Dooley wrote:
> > On Mon, Sep 29, 2025 at 04:06:24PM -0400, Kamal Dasu wrote:
> > > Adding brcmstb-hwspinlock bindings.
> > > 
> > > Signed-off-by: Kamal Dasu <kamal.dasu@broadcom.com>
> > > ---
> > >   .../hwlock/brcm,brcmstb-hwspinlock.yaml       | 36 +++++++++++++++++++
> > >   1 file changed, 36 insertions(+)
> > >   create mode 100644 Documentation/devicetree/bindings/hwlock/brcm,brcmstb-hwspinlock.yaml
> > > 
> > > diff --git a/Documentation/devicetree/bindings/hwlock/brcm,brcmstb-hwspinlock.yaml b/Documentation/devicetree/bindings/hwlock/brcm,brcmstb-hwspinlock.yaml
> > > new file mode 100644
> > > index 000000000000..f45399b4fe0b
> > > --- /dev/null
> > > +++ b/Documentation/devicetree/bindings/hwlock/brcm,brcmstb-hwspinlock.yaml
> > > @@ -0,0 +1,36 @@
> > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > > +%YAML 1.2
> > > +---
> > > +$id: http://devicetree.org/schemas/hwlock/brcm,brcmstb-hwspinlock.yaml#
> > > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > > +
> > > +title: Broadcom settop Hardware Spinlock
> > > +
> > > +maintainers:
> > > +  - Kamal Dasu <kamal.dasu@broadcom.com>
> > > +
> > > +properties:
> > > +  compatible:
> > > +    const: brcm,brcmstb-hwspinlock
> > 
> > Is "brcmstb" actually the name of a single platform?
> > Looking at the "brcmstb" pci binding, it looks like there's a whole load
> > of different devices there and none use "brcmstb":
> >            - brcm,bcm2711-pcie # The Raspberry Pi 4
> >            - brcm,bcm2712-pcie # Raspberry Pi 5
> >            - brcm,bcm4908-pcie
> >            - brcm,bcm7211-pcie # Broadcom STB version of RPi4
> >            - brcm,bcm7216-pcie # Broadcom 7216 Arm
> >            - brcm,bcm7278-pcie # Broadcom 7278 Arm
> >            - brcm,bcm7425-pcie # Broadcom 7425 MIPs
> >            - brcm,bcm7435-pcie # Broadcom 7435 MIPs
> >            - brcm,bcm7445-pcie # Broadcom 7445 Arm
> >            - brcm,bcm7712-pcie # Broadcom STB sibling of Rpi 5
> > 
> > If "stb" means "set top box", it sounds like a catchall for disparate
> > devices, which isn't permitted.
> 
> Unlike PCIe, the HW spinlock hardware has been stable across all Set-top box
> chips ever since it was added, which is why the catch all is IMHO adequate
> here.

I see. Now that I look more, there are other places where "stb" is used.
Sounds like "brcmstb" as generic fallback would probably be okay then.
Either way, the duplicate 1/3 patch needs to be sorted out.

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Re: [PATCH 1/3] dt-bindings: hwlock: support for brcmstb-hwspinlock

[Kamal Dasu]

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I see that, do you want me to send a v2 of the entire series ?.

On Tue, Sep 30, 2025 at 3:04 PM Conor Dooley <conor@kernel.org> wrote:
>
> On Mon, Sep 29, 2025 at 04:06:25PM -0400, Kamal Dasu wrote:
> > Adding brcmstb-hwspinlock bindings.
> >
> > Signed-off-by: Kamal Dasu <kamal.dasu@broadcom.com>
>
> You have two 1/3 patches in this series.
>
> > ---
> >  .../hwlock/brcm,brcmstb-hwspinlock.yaml       | 36 +++++++++++++++++++
> >  1 file changed, 36 insertions(+)
> >  create mode 100644 Documentation/devicetree/bindings/hwlock/brcm,brcmstb-hwspinlock.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/hwlock/brcm,brcmstb-hwspinlock.yaml b/Documentation/devicetree/bindings/hwlock/brcm,brcmstb-hwspinlock.yaml
> > new file mode 100644
> > index 000000000000..f45399b4fe0b
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/hwlock/brcm,brcmstb-hwspinlock.yaml
> > @@ -0,0 +1,36 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/hwlock/brcm,brcmstb-hwspinlock.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Broadcom settop Hardware Spinlock
> > +
> > +maintainers:
> > +  - Kamal Dasu <kamal.dasu@broadcom.com>
> > +
> > +properties:
> > +  compatible:
> > +    const: brcm,brcmstb-hwspinlock
> > +
> > +  "#hwlock-cells":
> > +    const: 1
> > +
> > +  reg:
> > +    maxItems: 1
> > +
> > +required:
> > +  - compatible
> > +  - reg
> > +  - "#hwlock-cells"
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > +  - |
> > +    hwlock@8404038 {
> > +        compatible = "brcm,brcmstb-hwspinlock";
> > +        reg = <0x8404038 0x40>;
> > +        #hwlock-cells = <1>;
> > +    };
> > +
> > --
> > 2.34.1
> >

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Re: [PATCH 2/3] hwspinlock: brcmstb hardware semaphore support

[Peng Fan]

On Mon, Sep 29, 2025 at 04:06:26PM -0400, Kamal Dasu wrote:
>Added support for brmstb_hwspinlock driver that makes use of
>the hwspinlock framework. Driver uses SUN_TOP_CTRL_SEMAPHORE_[1:15]
>registers to implement the hardware semaphore. With this change
>other brcmstb drivers can use hwspin_trylock() and hwspin_unlock()
>apis and make use of this hwspinlock framework. Other driver dt nodes
>just need to use a reference to the &hwspinlock and the lock id
>they want to use.
>e.g. hwlocks = <&hwspinlock0 0>;
>
>Signed-off-by: Kamal Dasu <kamal.dasu@broadcom.com>
>---
> drivers/hwspinlock/Kconfig              |  9 +++
> drivers/hwspinlock/Makefile             |  1 +
> drivers/hwspinlock/brcmstb_hwspinlock.c | 98 +++++++++++++++++++++++++
> 3 files changed, 108 insertions(+)
> create mode 100644 drivers/hwspinlock/brcmstb_hwspinlock.c
>
>diff --git a/drivers/hwspinlock/Kconfig b/drivers/hwspinlock/Kconfig
>index 3874d15b0e9b..551afa8df2d0 100644
>--- a/drivers/hwspinlock/Kconfig
>+++ b/drivers/hwspinlock/Kconfig
>@@ -63,4 +63,13 @@ config HSEM_U8500
> 
> 	  If unsure, say N.
> 
>+config HWSPINLOCK_BRCMSTB

Should be put above "config HWSPINLOCK_OMAP" to follow the order.

>+	tristate "Broadcom Setttop Hardware Semaphore functionality"
...
>--- a/drivers/hwspinlock/Makefile
>+++ b/drivers/hwspinlock/Makefile
>@@ -10,3 +10,4 @@ obj-$(CONFIG_HWSPINLOCK_SPRD)		+= sprd_hwspinlock.o
> obj-$(CONFIG_HWSPINLOCK_STM32)		+= stm32_hwspinlock.o
> obj-$(CONFIG_HWSPINLOCK_SUN6I)		+= sun6i_hwspinlock.o
> obj-$(CONFIG_HSEM_U8500)		+= u8500_hsem.o
>+obj-$(CONFIG_HWSPINLOCK_BRCMSTB)	+= brcmstb_hwspinlock.o

Put above "obj-$(CONFIG_HWSPINLOCK_OMAP)           += omap_hwspinlock.o"

>diff --git a/drivers/hwspinlock/brcmstb_hwspinlock.c b/drivers/hwspinlock/brcmstb_hwspinlock.c
>new file mode 100644
>index 000000000000..56206431a94c
>--- /dev/null
>+++ b/drivers/hwspinlock/brcmstb_hwspinlock.c
>@@ -0,0 +1,98 @@
>+// SPDX-License-Identifier: GPL-2.0
>+/*
>+ * brcmstb HWSEM driver
>+ *
>+ * Copyright (C) 2025 Broadcom
>+ *
>+ */
>+
>+#include <linux/module.h>
>+#include <linux/delay.h>
>+#include <linux/io.h>
>+#include <linux/slab.h>
>+#include <linux/spinlock.h>
>+#include <linux/hwspinlock.h>
>+#include <linux/platform_device.h>
>+#include <linux/mod_devicetable.h>

Sort the included headers.

>+#include "hwspinlock_internal.h"
>+
>+#define BRCMSTB_MAX_SEMAPHORES		16
>+#define RESET_SEMAPHORE			0
>+
>+#define HWSPINLOCK_VAL			'L'
>+
>+static int brcmstb_hwspinlock_trylock(struct hwspinlock *lock)
>+{
>+	void __iomem *lock_addr = (void __iomem *)lock->priv;
>+
>+	writel(HWSPINLOCK_VAL, lock_addr);
>+
>+	return (readl(lock_addr) == HWSPINLOCK_VAL);
>+}
>+
>+static void brcmstb_hwspinlock_unlock(struct hwspinlock *lock)
>+{
>+	void __iomem *lock_addr = (void __iomem *)lock->priv;
>+
>+	/* release the lock by writing 0 to it */
>+	writel(RESET_SEMAPHORE, lock_addr);
>+}
>+
>+static void brcmstb_hwspinlock_relax(struct hwspinlock *lock)
>+{
>+	ndelay(50);
>+}
>+
>+static const struct hwspinlock_ops brcmstb_hwspinlock_ops = {
>+	.trylock	= brcmstb_hwspinlock_trylock,
>+	.unlock		= brcmstb_hwspinlock_unlock,
>+	.relax		= brcmstb_hwspinlock_relax,
>+};
>+
>+static int brcmstb_hwspinlock_probe(struct platform_device *pdev)
>+{
>+	struct hwspinlock_device *bank;
>+	struct hwspinlock *hwlock;
>+	void __iomem *io_base;
>+	int i, num_locks = BRCMSTB_MAX_SEMAPHORES;
>+
>+	io_base = devm_platform_ioremap_resource(pdev, 0);
>+	if (IS_ERR(io_base)) {
>+		dev_err(&pdev->dev, "semaphore iobase mapping error\n");
>+		return PTR_ERR(io_base);
>+	}
>+
>+	bank = devm_kzalloc(&pdev->dev, struct_size(bank, lock, num_locks),
>+			    GFP_KERNEL);
>+	if (!bank)
>+		return -ENOMEM;
>+
>+	platform_set_drvdata(pdev, bank);

I not see users of drvdata in this driver, is this needed or I miss something?

>+
>+	for (i = 0, hwlock = &bank->lock[0]; i < num_locks; i++, hwlock++)
>+		hwlock->priv = (void __iomem *)(io_base + sizeof(u32) * i);
>+
>+	return devm_hwspin_lock_register(&pdev->dev, bank,
>+					 &brcmstb_hwspinlock_ops,
>+					 0, num_locks);

Seems all "brcm,brcmstb-hwspinlock" compatible devices have 16 sema locks.
If this is true, it is ok. Otherwise better not fix num_locks to
BRCMSTB_MAX_SEMAPHORES. "MAX" implys that not all devices have 16 sema locks.

Thanks,
Peng

Re: [PATCH 1/3] dt-bindings: hwlock: Adding brcmstb-hwspinlock support

[Peng Fan]

On Mon, Sep 29, 2025 at 04:06:24PM -0400, Kamal Dasu wrote:
>Adding brcmstb-hwspinlock bindings.
>
>Signed-off-by: Kamal Dasu <kamal.dasu@broadcom.com>
>---
> .../hwlock/brcm,brcmstb-hwspinlock.yaml       | 36 +++++++++++++++++++
> 1 file changed, 36 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/hwlock/brcm,brcmstb-hwspinlock.yaml
>
>+  - |
>+    hwlock@8404038 {
>+        compatible = "brcm,brcmstb-hwspinlock";
>+        reg = <0x8404038 0x40>;

Just have a question:
the base is not 64KB aligned, so just want to know is this module part of
the other ip block?

Thanks,
Peng

>+        #hwlock-cells = <1>;
>+    };
>+
>-- 
>2.34.1
>

Re: [PATCH 1/3] dt-bindings: hwlock: Adding brcmstb-hwspinlock support

[Kamal Dasu]

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On Tue, Sep 30, 2025 at 9:46 PM Peng Fan <peng.fan@oss.nxp.com> wrote:
>
> On Mon, Sep 29, 2025 at 04:06:24PM -0400, Kamal Dasu wrote:
> >Adding brcmstb-hwspinlock bindings.
> >
> >Signed-off-by: Kamal Dasu <kamal.dasu@broadcom.com>
> >---
> > .../hwlock/brcm,brcmstb-hwspinlock.yaml       | 36 +++++++++++++++++++
> > 1 file changed, 36 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/hwlock/brcm,brcmstb-hwspinlock.yaml
> >
> >+  - |
> >+    hwlock@8404038 {
> >+        compatible = "brcm,brcmstb-hwspinlock";
> >+        reg = <0x8404038 0x40>;
>
> Just have a question:
> the base is not 64KB aligned, so just want to know is this module part of
> the other ip block?
>
Yes this part of other ip block.


> Thanks,
> Peng
>
> >+        #hwlock-cells = <1>;
> >+    };
> >+
> >--
> >2.34.1
> >

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Re: [PATCH 1/3] dt-bindings: hwlock: Adding brcmstb-hwspinlock support

[Florian Fainelli]

On 9/30/2025 7:58 PM, Peng Fan wrote:
> On Mon, Sep 29, 2025 at 04:06:24PM -0400, Kamal Dasu wrote:
>> Adding brcmstb-hwspinlock bindings.
>>
>> Signed-off-by: Kamal Dasu <kamal.dasu@broadcom.com>
>> ---
>> .../hwlock/brcm,brcmstb-hwspinlock.yaml       | 36 +++++++++++++++++++
>> 1 file changed, 36 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/hwlock/brcm,brcmstb-hwspinlock.yaml
>>
>> +  - |
>> +    hwlock@8404038 {
>> +        compatible = "brcm,brcmstb-hwspinlock";
>> +        reg = <0x8404038 0x40>;
> 
> Just have a question:
> the base is not 64KB aligned, so just want to know is this module part of
> the other ip block?

The alignment is relevant to determine whether this is part of a larger 
IP block or not, though I am not sure why you use 64KB as a criteria. 
Our HW rules are to match the highest OS available page size for the 
systems, for us it used to be 4KB and is now 16KB alignment.

The block is part of a "sundry" IP which has lots of controls that did 
not belong anywhere else, for better or for worse (pin/mux controls, SoC 
identification, drive strength, reset controls, and other misc bits).
-- 
Florian

RE: [PATCH 1/3] dt-bindings: hwlock: Adding brcmstb-hwspinlock support

[Peng Fan]

> Subject: Re: [PATCH 1/3] dt-bindings: hwlock: Adding brcmstb-
> hwspinlock support
> 
> 
> 
> On 9/30/2025 7:58 PM, Peng Fan wrote:
> > On Mon, Sep 29, 2025 at 04:06:24PM -0400, Kamal Dasu wrote:
> >> Adding brcmstb-hwspinlock bindings.
> >>
> >> Signed-off-by: Kamal Dasu <kamal.dasu@broadcom.com>
> >> ---
> >> .../hwlock/brcm,brcmstb-hwspinlock.yaml       | 36
> +++++++++++++++++++
> >> 1 file changed, 36 insertions(+)
> >> create mode 100644
> >> Documentation/devicetree/bindings/hwlock/brcm,brcmstb-
> hwspinlock.yaml
> >>
> >> +  - |
> >> +    hwlock@8404038 {
> >> +        compatible = "brcm,brcmstb-hwspinlock";
> >> +        reg = <0x8404038 0x40>;
> >
> > Just have a question:
> > the base is not 64KB aligned, so just want to know is this module part
> > of the other ip block?
> 
> The alignment is relevant to determine whether this is part of a larger
> IP block or not, though I am not sure why you use 64KB as a criteria.
> Our HW rules are to match the highest OS available page size for the
> systems, for us it used to be 4KB and is now 16KB alignment.

Sorry for late. Typically an IP block starts at offset 64KB, but 4KB or 16KB
is also ok.

Thanks,
Peng.

> 
> The block is part of a "sundry" IP which has lots of controls that did not
> belong anywhere else, for better or for worse (pin/mux controls, SoC
> identification, drive strength, reset controls, and other misc bits).
> --
> Florian
>