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Wed, 22 Apr 2026 18:33:50 +0800 (CST) Message-ID: <1c1025c1-ead7-49fe-b18e-0454119d85f8@cixtech.com> Date: Wed, 22 Apr 2026 18:33:49 +0800 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v6 1/2] dma: arm-dma350: enable ANYCH interrupt for shared IRQ wiring To: Frank Li Cc: peter.chen@cixtech.com, fugang.duan@cixtech.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, vkoul@kernel.org, ychuang3@nuvoton.com, schung@nuvoton.com, robin.murphy@arm.com, Frank.Li@kernel.org, dmaengine@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, cix-kernel-upstream@cixtech.com, linux-arm-kernel@lists.infradead.org References: <20260325112159.663881-1-jun.guo@cixtech.com> <20260325112159.663881-2-jun.guo@cixtech.com> <932db8ad-a9d8-47ff-bf3c-62a54c42bb76@cixtech.com> Content-Language: en-US From: Jun Guo In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: OSA0EPF000000CC:EE_|PUZPR06MB5982:EE_ X-MS-Office365-Filtering-Correlation-Id: f59b8d3d-2c49-4fbe-8e73-08dea05aa5b3 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|7416014|376014|1800799024|36860700016|22082099003|56012099003|18002099003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: E6QyIMqtbUeamiLWTTm0mMXVVtExWz7ifIeCVTbFkVs8RmiD5TldJPvmosYyPe9ACXMeVEu6++gjgBjQM/hRyJAMqWoyK0SeaY7fpNx9H4dbz5GLqxPLkqXmu4xncXGU8eJSXwYKF0H/Y7wQBf3Wb+Xxh5MAaybRvE4yiwKK4lU/wIEECtlN50u/SFuhy6AaAn/e+Dau7Jk3A09UrxixQNGy3ZK+Sk73PV1+IH5xBJzrSs8tA6Hgz+kJRjQtwnH9SAqsM1YLbcJ5T0ec3MsAKmIEKPVEpiXVQgw+vJ/m48CwXMYk3vKBG/Qs6/BmxfurLvGvrMz1r6WKlgVZim2dwuhipJqm6pqP6q+PwDqXHZIpYlUblTwM3cxmY4Qg8PMva6eJ7weScr8L+Dem7RHAzGMpE94NvUNz1+6Mn3Jo1ytbSpsBtr8NIo6vxxFuPqgD X-OriginatorOrg: cixtech.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Apr 2026 10:33:51.8241 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f59b8d3d-2c49-4fbe-8e73-08dea05aa5b3 X-MS-Exchange-CrossTenant-Id: 0409f77a-e53d-4d23-943e-ccade7cb4811 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=0409f77a-e53d-4d23-943e-ccade7cb4811;Ip=[222.71.101.198];Helo=[smtprelay.cixcomputing.com] X-MS-Exchange-CrossTenant-AuthSource: OSA0EPF000000CC.apcprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PUZPR06MB5982 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260422_033403_128108_286ECA7B X-CRM114-Status: GOOD ( 19.67 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 4/22/2026 5:54 PM, Frank Li wrote: > [Some people who received this message don't often get email from frank.li@nxp.com. Learn why this is important at https://aka.ms/LearnAboutSenderIdentification ] > > EXTERNAL EMAIL > > On Tue, Apr 21, 2026 at 03:24:11PM +0800, Jun Guo wrote: >> Hi Robin, >> >> Just pinging. I’d like to ask if you have any comments on the latest patch? >> >> On 3/25/2026 7:21 PM, Jun Guo wrote: >>> Enable DMANSECCTRL.INTREN_ANYCHINTR during probe so channel >>> interrupts are propagated when integrators wire DMA-350 channels >>> onto a shared IRQ line. > > Your tag is wrong > > dmaegine: arm-dma350: enable ANYCH ... Okay, I'll fix this in the next version. > >>> >>> Signed-off-by: Jun Guo >>> --- >>> drivers/dma/arm-dma350.c | 9 +++++++++ >>> 1 file changed, 9 insertions(+) >>> >>> diff --git a/drivers/dma/arm-dma350.c b/drivers/dma/arm-dma350.c >>> index 84220fa83029..09403aca8bb0 100644 >>> --- a/drivers/dma/arm-dma350.c >>> +++ b/drivers/dma/arm-dma350.c >>> @@ -13,6 +13,11 @@ >>> #include "dmaengine.h" >>> #include "virt-dma.h" > > extra empty line between header file and macro The space actually exists in the code, but it is hidden in the review records. > > >>> +#define DMANSECCTRL 0x200 >>> + >>> +#define NSEC_CTRL 0x0c > > why need two layer regiser define, your use DMANSECCTRL + NSEC_CTRL， > > why not use one macro for 0x20c > DMANSECCTRL is the base address for a set of control registers. Currently, only the NSEC_CTRL register within that set is being used. All other registers in the same group share this same base address, and a similar arrangement applies to DMAINFO. > >>> +#define INTREN_ANYCHINTR_EN BIT(0) >>> + >>> #define DMAINFO 0x0f00 >>> #define DMA_BUILDCFG0 0xb0 >>> @@ -582,6 +587,10 @@ static int d350_probe(struct platform_device *pdev) >>> dmac->dma.device_issue_pending = d350_issue_pending; >>> INIT_LIST_HEAD(&dmac->dma.channels); >>> + reg = readl_relaxed(base + DMANSECCTRL + NSEC_CTRL); >>> + writel_relaxed(reg | INTREN_ANYCHINTR_EN, >>> + base + DMANSECCTRL + NSEC_CTRL); >>> + >>> /* Would be nice to have per-channel caps for this... */ >>> memset = true; >>> for (int i = 0; i < nchan; i++) { >>