From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id ED85BC46467 for ; Tue, 10 Jan 2023 08:07:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:From:References:Cc:To: Subject:MIME-Version:Date:Message-ID:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=4UG3yyXp53xZwI3cjPSV5nk3LkEJ+0rQ4lrL9mp8goI=; b=LlnoRZic8Z6CP/ rHsU9fp3z6XScFiXLKyEEWfeNaycy7PW3xgxyXNodMZ+JtbhS3Rs7ZEdm/Wkf51FhHITJS8+opb8t O6NxcKjGoOVs8wYRsrWn+yDUDeaBj1Dcq9C3oog9sYnocqYW9MkcgNRRDfdLTJreI24LAhwSbAMM1 k44r2Hcfe2P6LqmFmMdzyjxRdxX2y3XT/Jpp4Aqc0w6B03Z8XksxSN1ufhIfRwOCYfx++xnGFGT21 Wv5V5O+ANhBzH3wwXuCwDQs/ntiVOSEKQFn3H7MIJ954oNeHK8R78ev0irDUaYASJoKo9sYlrs54y 048cMwyr6NB+N3em+1aw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1pF9dz-005hco-6d; Tue, 10 Jan 2023 08:06:03 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1pF9du-005hac-SW for linux-arm-kernel@lists.infradead.org; Tue, 10 Jan 2023 08:06:01 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 9AF50AD7; Tue, 10 Jan 2023 00:06:37 -0800 (PST) Received: from [10.162.42.6] (unknown [10.162.42.6]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 26F9A3F67D; Tue, 10 Jan 2023 00:05:48 -0800 (PST) Message-ID: <1c555737-b2a6-cde0-8690-0278a75aa572@arm.com> Date: Tue, 10 Jan 2023 13:35:46 +0530 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.2.2 Subject: Re: [PATCH v4 3/8] arm64/sysreg: Convert SPE registers to automatic generation Content-Language: en-US To: Rob Herring , Peter Zijlstra , Will Deacon , Mark Rutland , Catalin Marinas , Marc Zyngier , James Morse , Alexandru Elisei , Suzuki K Poulose , Oliver Upton , Ingo Molnar , Arnaldo Carvalho de Melo , Alexander Shishkin , Jiri Olsa , Namhyung Kim Cc: Mark Brown , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-perf-users@vger.kernel.org, James Clark References: <20220825-arm-spe-v8-7-v4-0-327f860daf28@kernel.org> <20220825-arm-spe-v8-7-v4-3-327f860daf28@kernel.org> From: Anshuman Khandual In-Reply-To: <20220825-arm-spe-v8-7-v4-3-327f860daf28@kernel.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230110_000559_049016_669B711F X-CRM114-Status: GOOD ( 19.05 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 1/10/23 00:56, Rob Herring wrote: > Convert all the SPE register defines to automatic generation. No > functional changes. > > New registers and fields for SPEv1.2 are added with the conversion. > > Some of the PMBSR MSS field defines are kept as the automatic generation > has no way to create multiple names for the same register bits. The > meaning of the MSS field depends on other bits. > > Tested-by: James Clark > Signed-off-by: Rob Herring Reviewed-by: Anshuman Khandual > --- > v4: > - Rebase on v6.2-rc1 > v3: > - Make some fields enums and add some missing fields > v2: > - New patch > --- > arch/arm64/include/asm/sysreg.h | 91 ++------------------------ > arch/arm64/tools/sysreg | 139 ++++++++++++++++++++++++++++++++++++++++ > 2 files changed, 144 insertions(+), 86 deletions(-) > > diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h > index dbb0e8e22cf4..db269eda7c1c 100644 > --- a/arch/arm64/include/asm/sysreg.h > +++ b/arch/arm64/include/asm/sysreg.h > @@ -216,99 +216,18 @@ > #define SYS_PAR_EL1_FST GENMASK(6, 1) > > /*** Statistical Profiling Extension ***/ > -/* ID registers */ > -#define SYS_PMSIDR_EL1 sys_reg(3, 0, 9, 9, 7) > -#define PMSIDR_EL1_FE_SHIFT 0 > -#define PMSIDR_EL1_FT_SHIFT 1 > -#define PMSIDR_EL1_FL_SHIFT 2 > -#define PMSIDR_EL1_ARCHINST_SHIFT 3 > -#define PMSIDR_EL1_LDS_SHIFT 4 > -#define PMSIDR_EL1_ERND_SHIFT 5 > -#define PMSIDR_EL1_INTERVAL_SHIFT 8 > -#define PMSIDR_EL1_INTERVAL_MASK GENMASK_ULL(11, 8) > -#define PMSIDR_EL1_MAXSIZE_SHIFT 12 > -#define PMSIDR_EL1_MAXSIZE_MASK GENMASK_ULL(15, 12) > -#define PMSIDR_EL1_COUNTSIZE_SHIFT 16 > -#define PMSIDR_EL1_COUNTSIZE_MASK GENMASK_ULL(19, 16) > - > -#define SYS_PMBIDR_EL1 sys_reg(3, 0, 9, 10, 7) > -#define PMBIDR_EL1_ALIGN_SHIFT 0 > -#define PMBIDR_EL1_ALIGN_MASK 0xfU > -#define PMBIDR_EL1_P_SHIFT 4 > -#define PMBIDR_EL1_F_SHIFT 5 > - > -/* Sampling controls */ > -#define SYS_PMSCR_EL1 sys_reg(3, 0, 9, 9, 0) > -#define PMSCR_EL1_E0SPE_SHIFT 0 > -#define PMSCR_EL1_E1SPE_SHIFT 1 > -#define PMSCR_EL1_CX_SHIFT 3 > -#define PMSCR_EL1_PA_SHIFT 4 > -#define PMSCR_EL1_TS_SHIFT 5 > -#define PMSCR_EL1_PCT_SHIFT 6 > - > -#define SYS_PMSCR_EL2 sys_reg(3, 4, 9, 9, 0) > -#define PMSCR_EL2_E0HSPE_SHIFT 0 > -#define PMSCR_EL2_E2SPE_SHIFT 1 > -#define PMSCR_EL2_CX_SHIFT 3 > -#define PMSCR_EL2_PA_SHIFT 4 > -#define PMSCR_EL2_TS_SHIFT 5 > -#define PMSCR_EL2_PCT_SHIFT 6 > - > -#define SYS_PMSICR_EL1 sys_reg(3, 0, 9, 9, 2) > - > -#define SYS_PMSIRR_EL1 sys_reg(3, 0, 9, 9, 3) > -#define PMSIRR_EL1_RND_SHIFT 0 > -#define PMSIRR_EL1_INTERVAL_SHIFT 8 > -#define PMSIRR_EL1_INTERVAL_MASK GENMASK_ULL(31, 8) > - > -/* Filtering controls */ > -#define SYS_PMSNEVFR_EL1 sys_reg(3, 0, 9, 9, 1) > - > -#define SYS_PMSFCR_EL1 sys_reg(3, 0, 9, 9, 4) > -#define PMSFCR_EL1_FE_SHIFT 0 > -#define PMSFCR_EL1_FT_SHIFT 1 > -#define PMSFCR_EL1_FL_SHIFT 2 > -#define PMSFCR_EL1_B_SHIFT 16 > -#define PMSFCR_EL1_LD_SHIFT 17 > -#define PMSFCR_EL1_ST_SHIFT 18 > - > -#define SYS_PMSEVFR_EL1 sys_reg(3, 0, 9, 9, 5) > #define PMSEVFR_EL1_RES0_IMP \ > (GENMASK_ULL(47, 32) | GENMASK_ULL(23, 16) | GENMASK_ULL(11, 8) |\ > BIT_ULL(6) | BIT_ULL(4) | BIT_ULL(2) | BIT_ULL(0)) > #define PMSEVFR_EL1_RES0_V1P1 \ > (PMSEVFR_EL1_RES0_IMP & ~(BIT_ULL(18) | BIT_ULL(17) | BIT_ULL(11))) > > -#define SYS_PMSLATFR_EL1 sys_reg(3, 0, 9, 9, 6) > -#define PMSLATFR_EL1_MINLAT_SHIFT 0 > - > -/* Buffer controls */ > -#define SYS_PMBLIMITR_EL1 sys_reg(3, 0, 9, 10, 0) > -#define PMBLIMITR_EL1_E_SHIFT 0 > -#define PMBLIMITR_EL1_FM_SHIFT 1 > -#define PMBLIMITR_EL1_FM_MASK GENMASK_ULL(2, 1) > -#define PMBLIMITR_EL1_FM_STOP_IRQ 0 > - > -#define SYS_PMBPTR_EL1 sys_reg(3, 0, 9, 10, 1) > - > /* Buffer error reporting */ > -#define SYS_PMBSR_EL1 sys_reg(3, 0, 9, 10, 3) > -#define PMBSR_EL1_COLL_SHIFT 16 > -#define PMBSR_EL1_S_SHIFT 17 > -#define PMBSR_EL1_EA_SHIFT 18 > -#define PMBSR_EL1_DL_SHIFT 19 > -#define PMBSR_EL1_EC_SHIFT 26 > -#define PMBSR_EL1_EC_MASK GENMASK_ULL(31, 26) > - > -#define PMBSR_EL1_EC_BUF 0x0UL > -#define PMBSR_EL1_EC_FAULT_S1 0x24UL > -#define PMBSR_EL1_EC_FAULT_S2 0x25UL > - > -#define PMBSR_EL1_FAULT_FSC_SHIFT 0 > -#define PMBSR_EL1_FAULT_FSC_MASK 0x3fUL > - > -#define PMBSR_EL1_BUF_BSC_SHIFT 0 > -#define PMBSR_EL1_BUF_BSC_MASK 0x3fUL > +#define PMBSR_EL1_FAULT_FSC_SHIFT PMBSR_EL1_MSS_SHIFT > +#define PMBSR_EL1_FAULT_FSC_MASK PMBSR_EL1_MSS_MASK > + > +#define PMBSR_EL1_BUF_BSC_SHIFT PMBSR_EL1_MSS_SHIFT > +#define PMBSR_EL1_BUF_BSC_MASK PMBSR_EL1_MSS_MASK > > #define PMBSR_EL1_BUF_BSC_FULL 0x1UL > > diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg > index 184e58fd5631..c323833cf235 100644 > --- a/arch/arm64/tools/sysreg > +++ b/arch/arm64/tools/sysreg > @@ -1618,6 +1618,130 @@ Sysreg FAR_EL1 3 0 6 0 0 > Field 63:0 ADDR > EndSysreg > > +Sysreg PMSCR_EL1 3 0 9 9 0 > +Res0 63:8 > +Field 7:6 PCT > +Field 5 TS > +Field 4 PA > +Field 3 CX > +Res0 2 > +Field 1 E1SPE > +Field 0 E0SPE > +EndSysreg > + > +Sysreg PMSNEVFR_EL1 3 0 9 9 1 > +Field 63:0 E > +EndSysreg > + > +Sysreg PMSICR_EL1 3 0 9 9 2 > +Field 63:56 ECOUNT > +Res0 55:32 > +Field 31:0 COUNT > +EndSysreg > + > +Sysreg PMSIRR_EL1 3 0 9 9 3 > +Res0 63:32 > +Field 31:8 INTERVAL > +Res0 7:1 > +Field 0 RND > +EndSysreg > + > +Sysreg PMSFCR_EL1 3 0 9 9 4 > +Res0 63:19 > +Field 18 ST > +Field 17 LD > +Field 16 B > +Res0 15:4 > +Field 3 FnE > +Field 2 FL > +Field 1 FT > +Field 0 FE > +EndSysreg > + > +Sysreg PMSEVFR_EL1 3 0 9 9 5 > +Field 63:0 E > +EndSysreg > + > +Sysreg PMSLATFR_EL1 3 0 9 9 6 > +Res0 63:16 > +Field 15:0 MINLAT > +EndSysreg > + > +Sysreg PMSIDR_EL1 3 0 9 9 7 > +Res0 63:25 > +Field 24 PBT > +Field 23:20 FORMAT > +Enum 19:16 COUNTSIZE > + 0b0010 12_BIT_SAT > + 0b0011 16_BIT_SAT > +EndEnum > +Field 15:12 MAXSIZE > +Enum 11:8 INTERVAL > + 0b0000 256 > + 0b0010 512 > + 0b0011 768 > + 0b0100 1024 > + 0b0101 1536 > + 0b0110 2048 > + 0b0111 3072 > + 0b1000 4096 > +EndEnum > +Res0 7 > +Field 6 FnE > +Field 5 ERND > +Field 4 LDS > +Field 3 ARCHINST > +Field 2 FL > +Field 1 FT > +Field 0 FE > +EndSysreg > + > +Sysreg PMBLIMITR_EL1 3 0 9 10 0 > +Field 63:12 LIMIT > +Res0 11:6 > +Field 5 PMFZ > +Res0 4:3 > +Enum 2:1 FM > + 0b00 FILL > + 0b10 DISCARD > +EndEnum > +Field 0 E > +EndSysreg > + > +Sysreg PMBPTR_EL1 3 0 9 10 1 > +Field 63:0 PTR > +EndSysreg > + > +Sysreg PMBSR_EL1 3 0 9 10 3 > +Res0 63:32 > +Enum 31:26 EC > + 0b000000 BUF > + 0b100100 FAULT_S1 > + 0b100101 FAULT_S2 > + 0b011110 FAULT_GPC > + 0b011111 IMP_DEF > +EndEnum > +Res0 25:20 > +Field 19 DL > +Field 18 EA > +Field 17 S > +Field 16 COLL > +Field 15:0 MSS > +EndSysreg > + > +Sysreg PMBIDR_EL1 3 0 9 10 7 > +Res0 63:12 > +Enum 11:8 EA > + 0b0000 NotDescribed > + 0b0001 Ignored > + 0b0010 SError > +EndEnum > +Res0 7:6 > +Field 5 F > +Field 4 P > +Field 3:0 ALIGN > +EndSysreg > + > SysregFields CONTEXTIDR_ELx > Res0 63:32 > Field 31:0 PROCID > @@ -1772,6 +1896,21 @@ Sysreg FAR_EL2 3 4 6 0 0 > Field 63:0 ADDR > EndSysreg > > +Sysreg PMSCR_EL2 3 4 9 9 0 > +Res0 63:8 > +Enum 7:6 PCT > + 0b00 VIRT > + 0b01 PHYS > + 0b11 GUEST > +EndEnum > +Field 5 TS > +Field 4 PA > +Field 3 CX > +Res0 2 > +Field 1 E2SPE > +Field 0 E0HSPE > +EndSysreg > + > Sysreg CONTEXTIDR_EL2 3 4 13 0 1 > Fields CONTEXTIDR_ELx > EndSysreg > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel