SMP enablement on Cortex-R52 (using PSCI ?)

[Ayan Kumar Halder <ayankuma@amd.com>]

Hi PSCI developers,

We have a SoC where there are 4 Cortex-R52 which is distributed in two 
clusters. So we have 2 Cortex-R52 in one cluster and 2 Cortex-R52 in 
another cluster.

We wish to enable SMP on the 2 R52 within a cluster with Xen hypervisor 
(EL2 software) running on them.

We are trying to explore if we can use PSCI for booting the secondary cores.

Refer Cortex-R52 TRM 
(https://developer.arm.com/documentation/100026/0101/?lang=en ), it 
specifies the following :-

Page 24 - Section 1.4.1

"Support for Exception levels, EL0, EL1, and EL2."

Page 30 - Section 2.1.6

"The Cortex-R52 processor does not implement TrustZone® technology. It 
does not support the ability to distinguish between secure and 
non-secure physical memories."

Thus, there is no EL3 and secure world in Cortex-R52. It implements 
AArch32-V8R architecture.


Refer PSCI design document, 
https://developer.arm.com/documentation/den0022/e/?lang=en

Page 18 -
"The PSCI specification focuses on the interface between Security states 
for power management. It provides a method for issuing power management 
requests. To deal with the requests, the PPF must include a PSCI 
implementation. A PSCI implementation might require communication 
between the PPF and a Trusted OS or SP."

Page 17 - Privileged Platform Firmware (PPF)

"For Armv7 systems, or Armv8 systems using AArch32 at EL3, PPF executes 
in EL3."

 From the above two statements, I infer that PSCI requires a PPF 
(running at EL3) and a Trusted OS (running at secure EL2). If this is 
correct, then R52  cannot support PSCI. Please correct me if I am mistaken.

I wish to know how do we wake up the secondary core if PSCI is not 
supported.

Kind regards,
Ayan




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