From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.5 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,NICE_REPLY_A,SPF_HELO_NONE,SPF_PASS, USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 57C08C47082 for ; Mon, 7 Jun 2021 10:49:32 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id DF9B261073 for ; Mon, 7 Jun 2021 10:49:31 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org DF9B261073 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=hisilicon.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:Date: Message-ID:From:References:CC:To:Subject:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=PzOqndCm2QhlScbiwFty7cX1KVTml2ztMAwiTAABxEU=; b=JtLpjeXbUWAZ8Q2Dd80ntiVaPb 5f34FDuhsJr8ZVkzyHwPUt8pfNWGAU3ThRRCjIWGNQFWB4iNPhdgIhJH7qDlR+ujmRAVib958arv4 qiL+VRUbEm2y4ptsk+TkMdHSH3pmbRyXOO0IDOT/eSeDSg9NtX/Dg+DCGba4ih2nlwPtEDo+oDItk b1QuedfM6vyshRnE6Hz7s/WXYxl5T+fn+7cGO8c09JyBbHLj8DX4djRLqYTEbvjcO9z8vcFwXQFq0 XVi4TEXiFYH3Mn7AnYbm9m98Y3jw8F1gceZUvBugiFD1WR7sviFGXqQKlQJfzhjdFTacaqE29MI7Q 8WU8U5DA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1lqCmq-003347-1m; Mon, 07 Jun 2021 10:47:16 +0000 Received: from szxga02-in.huawei.com ([45.249.212.188]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1lqCfA-0030DY-MR for linux-arm-kernel@lists.infradead.org; Mon, 07 Jun 2021 10:39:25 +0000 Received: from dggemv704-chm.china.huawei.com (unknown [172.30.72.53]) by szxga02-in.huawei.com (SkyGuard) with ESMTP id 4Fz8t435Jyz6wXC; Mon, 7 Jun 2021 18:36:12 +0800 (CST) Received: from dggpeml500023.china.huawei.com (7.185.36.114) by dggemv704-chm.china.huawei.com (10.3.19.47) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.2; Mon, 7 Jun 2021 18:39:14 +0800 Received: from [10.67.77.175] (10.67.77.175) by dggpeml500023.china.huawei.com (7.185.36.114) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.2; Mon, 7 Jun 2021 18:39:14 +0800 Subject: Re: [PATCH -next] arm64: perf: Fix hw_event_id check in __armv8_pmuv3_map_event To: Mark Rutland CC: , Will Deacon References: <1623050343-62397-1-git-send-email-zhangshaokun@hisilicon.com> <20210607083704.GA97489@C02TD0UTHF1T.local> From: Shaokun Zhang Message-ID: <1cd71c4a-594b-8a39-b6f8-01146348a512@hisilicon.com> Date: Mon, 7 Jun 2021 18:39:14 +0800 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:78.0) Gecko/20100101 Thunderbird/78.8.1 MIME-Version: 1.0 In-Reply-To: <20210607083704.GA97489@C02TD0UTHF1T.local> Content-Language: en-US X-Originating-IP: [10.67.77.175] X-ClientProxiedBy: dggems705-chm.china.huawei.com (10.3.19.182) To dggpeml500023.china.huawei.com (7.185.36.114) X-CFilter-Loop: Reflected X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210607_033920_956978_C318D147 X-CRM114-Status: GOOD ( 19.19 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Mark, On 2021/6/7 16:37, Mark Rutland wrote: > On Mon, Jun 07, 2021 at 03:19:03PM +0800, Shaokun Zhang wrote: >> Raw event SW_INCR (0x0000) shall be included in this check, so fix it. >> >> Cc: Mark Rutland >> Cc: Will Deacon >> Signed-off-by: Shaokun Zhang > > Given that SW_INCR depends on the specific counter used (and userspace > has no control over this), I don't think that it makes sense to expose > to userspace, much like CHAIN, so I suspect it's better to update the > commentary instead. Indeed, no harm on perf use. > > Do you have a need for SW_INCR, or was this found by inspection? > By inspection, when I traced some other thing and noticed that the event 0x0000 was exclusive in the if condition by accident. Thanks, Shaokun > Thanks, > Mark. > >> --- >> arch/arm64/kernel/perf_event.c | 2 +- >> 1 file changed, 1 insertion(+), 1 deletion(-) >> >> diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c >> index a661010308c0..fa2f60d09e15 100644 >> --- a/arch/arm64/kernel/perf_event.c >> +++ b/arch/arm64/kernel/perf_event.c >> @@ -1000,7 +1000,7 @@ static int __armv8_pmuv3_map_event(struct perf_event *event, >> event->hw.flags |= ARMPMU_EVT_64BIT; >> >> /* Only expose micro/arch events supported by this PMU */ >> - if ((hw_event_id > 0) && (hw_event_id < ARMV8_PMUV3_MAX_COMMON_EVENTS) >> + if ((hw_event_id >= 0) && (hw_event_id < ARMV8_PMUV3_MAX_COMMON_EVENTS) >> && test_bit(hw_event_id, armpmu->pmceid_bitmap)) { >> return hw_event_id; >> } >> -- >> 2.7.4 >> > . > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel