From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4AA7CC2BD09 for ; Tue, 9 Jul 2024 12:56:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: Content-Type:In-Reply-To:From:References:Cc:To:Subject:MIME-Version:Date: Message-ID:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=KTVkyqNmu2VuQaptTyfTGILFf20gRp3SxItXNrnPiJw=; b=pOkGxpkNRZDzuzt1dSusEn1/q4 KEdVlsbAeT80/mnDNPYxYV+fmNVx/kw0Tkt8CNIBBXu0zXU1+6HNkO1tWn6e+D+m4Hl1MRu891vm6 FxJfPqIERGxiJTkqb8yIma3SbMD3fJeSDYz1Ll7pxO8XeuT9SaN1DaBptOFuJREiRWsQKd5HdIFJS sP9P4+aK8SBXZmmo8z/Tq9Lsh1RdkNtRxcqBIzPa7p2g0nA2gdnO5noS/vUz3Js0q8WzpJSqLD/We hGkbTNkX2W8BRTiFIF4yxvPBHPrRr6CMWwTFry9yHcLAZ3JKbfrHGMT2Tzc8oylxeU2Rb59kXmvAF JSE4Ttag==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sRANy-00000007D2N-3agv; Tue, 09 Jul 2024 12:55:58 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sRANj-00000007CzR-32Nc for linux-arm-kernel@lists.infradead.org; Tue, 09 Jul 2024 12:55:45 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 4B1E6153B; Tue, 9 Jul 2024 05:56:08 -0700 (PDT) Received: from [10.57.74.191] (unknown [10.57.74.191]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 30AFF3F766; Tue, 9 Jul 2024 05:55:40 -0700 (PDT) Message-ID: <1ce456b5-0652-4522-98ea-b32d96c1adf4@arm.com> Date: Tue, 9 Jul 2024 13:55:38 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 06/15] arm64: Make the PHYS_MASK_SHIFT dynamic Content-Language: en-GB To: Will Deacon , Steven Price Cc: kvm@vger.kernel.org, kvmarm@lists.linux.dev, Catalin Marinas , Marc Zyngier , James Morse , Oliver Upton , Zenghui Yu , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Joey Gouly , Alexandru Elisei , Christoffer Dall , Fuad Tabba , linux-coco@lists.linux.dev, Ganapatrao Kulkarni References: <20240701095505.165383-1-steven.price@arm.com> <20240701095505.165383-7-steven.price@arm.com> <20240709114337.GB13242@willie-the-truck> From: Suzuki K Poulose In-Reply-To: <20240709114337.GB13242@willie-the-truck> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240709_055543_875894_DA0C5AAF X-CRM114-Status: GOOD ( 20.84 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 09/07/2024 12:43, Will Deacon wrote: > On Mon, Jul 01, 2024 at 10:54:56AM +0100, Steven Price wrote: >> Make the PHYS_MASK_SHIFT dynamic for Realms. This is only is required >> for masking the PFN from a pte entry. For a realm phys_mask_shift is >> reduced if the RMM reports a smaller configured size for the guest. >> >> The realm configuration splits the address space into two with the top >> half being memory shared with the host, and the bottom half being >> protected memory. We treat the bit which controls this split as an >> attribute bit and hence exclude it (and any higher bits) from the mask. >> >> Co-developed-by: Suzuki K Poulose >> Signed-off-by: Suzuki K Poulose >> Signed-off-by: Steven Price >> >> --- >> v3: Drop the MAX_PHYS_MASK{,_SHIFT} definitions as they are no longer >> needed. >> --- >> arch/arm64/include/asm/pgtable-hwdef.h | 6 ------ >> arch/arm64/include/asm/pgtable.h | 5 +++++ >> arch/arm64/kernel/rsi.c | 5 +++++ >> 3 files changed, 10 insertions(+), 6 deletions(-) >> >> diff --git a/arch/arm64/include/asm/pgtable-hwdef.h b/arch/arm64/include/asm/pgtable-hwdef.h >> index 9943ff0af4c9..2e3af0693bd8 100644 >> --- a/arch/arm64/include/asm/pgtable-hwdef.h >> +++ b/arch/arm64/include/asm/pgtable-hwdef.h >> @@ -203,12 +203,6 @@ >> */ >> #define PTE_S2_MEMATTR(t) (_AT(pteval_t, (t)) << 2) >> >> -/* >> - * Highest possible physical address supported. >> - */ >> -#define PHYS_MASK_SHIFT (CONFIG_ARM64_PA_BITS) >> -#define PHYS_MASK ((UL(1) << PHYS_MASK_SHIFT) - 1) >> - >> #define TTBR_CNP_BIT (UL(1) << 0) >> >> /* >> diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgtable.h >> index f8efbc128446..11d614d83317 100644 >> --- a/arch/arm64/include/asm/pgtable.h >> +++ b/arch/arm64/include/asm/pgtable.h >> @@ -39,6 +39,11 @@ >> #include >> #include >> >> +extern unsigned int phys_mask_shift; >> + >> +#define PHYS_MASK_SHIFT (phys_mask_shift) >> +#define PHYS_MASK ((1UL << PHYS_MASK_SHIFT) - 1) > > I tried to figure out where this is actually used so I could understand > your comment in the commit message: > > > This is only is required for masking the PFN from a pte entry > > The closest thing I could find is in arch/arm64/mm/mmap.c, where the > mask is used as part of valid_mmap_phys_addr_range() which exists purely > to filter accesses to /dev/mem. That's pretty niche, so why not just > inline the RSI-specific stuff in there behind a static key instead of > changing these definitions? > > Or did I miss a subtle user somewhere else? We need to prevent ioremap() of addresses beyond that limit too. Suzuki > > Will