From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7EBEFEA4E3F for ; Mon, 2 Mar 2026 16:40:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: Content-Type:In-Reply-To:From:References:Cc:To:Subject:MIME-Version:Date: Message-ID:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=xaNX5Hi7NGdLaC4H5wS7wUwsdKzu5nKzOzI5YHMiI4c=; b=NrfvYQb8y4zAC3P3SZhiFv6V/N dzw4BxwewO54pp/fuWFWd7baaNZnoNSBU9O6sR9J3F3MTtyiBY16SSZ0UaH7X4DQpyajDYmkO/Spo 3uU/qrmdGTvB6s2f0Sxl9W3od/58VqbHOmxuCU5xi4W6e4EYuA0kcEslUtpPwTHGsFdbNDZQnQuvM nlVsJdD8G7SzPzMGi1dFO/yYkL34LzXfr8DYFO3qMfAC3QnJM9m06IZDz8fDbnPlYot1AD001IHCf nyjMpazd8vkqN1x77GjjfoEqvTscVwAQ/L3EOlKFZVwRotP2bBTCLojmQWraixu1eRPSrD1cGTxsi HIRiRrdw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98.2 #2 (Red Hat Linux)) id 1vx6KB-0000000DW6h-1MrG; Mon, 02 Mar 2026 16:40:51 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.98.2 #2 (Red Hat Linux)) id 1vx6K7-0000000DW5t-3yai for linux-arm-kernel@lists.infradead.org; Mon, 02 Mar 2026 16:40:49 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 0F69914BF; Mon, 2 Mar 2026 08:40:39 -0800 (PST) Received: from [10.57.82.202] (unknown [10.57.82.202]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 0D9363F694; Mon, 2 Mar 2026 08:40:42 -0800 (PST) Message-ID: <1e2db927-6ffd-40a1-9ff5-6713631e989b@arm.com> Date: Mon, 2 Mar 2026 17:40:41 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 2/2] arm64: dts: zena: Add support for Zena CSS To: Debbie Horsfall , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Liviu Dudau , Sudeep Holla , Lorenzo Pieralisi , Linus Walleij Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org References: <20260212-zena-css-v2-0-d33ea23cb9c2@arm.com> <20260212-zena-css-v2-2-d33ea23cb9c2@arm.com> Content-Language: en-US From: Andre Przywara In-Reply-To: <20260212-zena-css-v2-2-d33ea23cb9c2@arm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260302_084048_116392_E0D3E70F X-CRM114-Status: GOOD ( 18.99 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Debbie, On 2/12/26 12:16, Debbie Horsfall wrote: > Introduce the Zena CSS Fixed Virtual Platform (FVP) dts. This is > currently the only Zena CSS variant, however the common definitions are > included in a common dtsi for extensibility. Many thanks for the changes! I can confirm that the concerns I had on v1 have all been addressed. The other changes you did are indeed cosmetical: upper case/lower case conversions, and moving of nodes and properties. Thanks for addressing those coding style issues proactively! I checked the CPU nodes again: they match each other apart from the obvious differences due to the MPIDRs and cluster/cache numbers. Also the rest looks as reasonable as one could expect. > Signed-off-by: Debbie Horsfall Reviewed-by: Andre Przywara Cheers, Andre > --- > arch/arm64/boot/dts/arm/Makefile | 1 + > arch/arm64/boot/dts/arm/zena-css-fvp.dts | 55 +++ > arch/arm64/boot/dts/arm/zena-css.dtsi | 777 +++++++++++++++++++++++++++++++ > 3 files changed, 833 insertions(+) > > diff --git a/arch/arm64/boot/dts/arm/Makefile b/arch/arm64/boot/dts/arm/Makefile > index f30ee045dc95..770fb145b4a9 100644 > --- a/arch/arm64/boot/dts/arm/Makefile > +++ b/arch/arm64/boot/dts/arm/Makefile > @@ -8,3 +8,4 @@ dtb-$(CONFIG_ARCH_VEXPRESS) += vexpress-v2f-1xv7-ca53x2.dtb > dtb-$(CONFIG_ARCH_VEXPRESS) += fvp-base-revc.dtb > dtb-$(CONFIG_ARCH_VEXPRESS) += corstone1000-fvp.dtb corstone1000-mps3.dtb > dtb-$(CONFIG_ARCH_VEXPRESS) += morello-sdp.dtb morello-fvp.dtb > +dtb-$(CONFIG_ARCH_VEXPRESS) += zena-css-fvp.dtb > diff --git a/arch/arm64/boot/dts/arm/zena-css-fvp.dts b/arch/arm64/boot/dts/arm/zena-css-fvp.dts > new file mode 100644 > index 000000000000..b75204a91882 > --- /dev/null > +++ b/arch/arm64/boot/dts/arm/zena-css-fvp.dts > @@ -0,0 +1,55 @@ > +// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) > +/* > + * Copyright (c) 2025, Arm Limited. All rights reserved. > + */ > + > +/dts-v1/; > + > +#include "zena-css.dtsi" > + > +/ { > + model = "Zena CSS Fixed Virtual Platform"; > + compatible = "arm,zena-css-fvp", "arm,zena-css", "arm,vexpress"; > + > + chosen { > + stdout-path = &soc_serial0; > + }; > +}; > + > +&soc { > + virtio@30020000 { > + compatible = "virtio,mmio"; > + reg = <0x0 0x30020000 0x0 0x10000>; > + interrupts = ; > + }; > + > + virtio@30030000 { > + compatible = "virtio,mmio"; > + reg = <0x0 0x30030000 0x0 0x10000>; > + interrupts = ; > + }; > + > + virtio@30040000 { > + compatible = "virtio,mmio"; > + reg = <0x0 0x30040000 0x0 0x10000>; > + interrupts = ; > + }; > + > + virtio@30050000 { > + compatible = "virtio,mmio"; > + reg = <0x0 0x30050000 0x0 0x10000>; > + interrupts = ; > + }; > + > + virtio@30060000 { > + compatible = "virtio,mmio"; > + reg = <0x0 0x30060000 0x0 0x10000>; > + interrupts = ; > + }; > + > + virtio@30080000 { > + compatible = "virtio,mmio"; > + reg = <0x0 0x30080000 0x0 0x10000>; > + interrupts = ; > + }; > +}; > diff --git a/arch/arm64/boot/dts/arm/zena-css.dtsi b/arch/arm64/boot/dts/arm/zena-css.dtsi > new file mode 100644 > index 000000000000..9899d2883337 > --- /dev/null > +++ b/arch/arm64/boot/dts/arm/zena-css.dtsi > @@ -0,0 +1,777 @@ > +// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) > +/* > + * Copyright (c) 2025, Arm Limited. All rights reserved. > + */ > + > +#include > + > +/ { > + #address-cells = <2>; > + #size-cells = <2>; > + interrupt-parent = <&gic>; > + > + soc_clk24mhz: clock-24000000 { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <24000000>; > + clock-output-names = "refclk24mhz"; > + }; > + > + cpus { > + #address-cells = <2>; > + #size-cells = <0>; > + > + /* > + * The latency and residency numbers below are for illustrative > + * purposes only and may vary on actual silicon. These values are > + * considered just to demonstrate that the cpuidle governor logic > + * works. > + */ > + idle-states { > + entry-method = "psci"; > + > + cpu_sleep: cpu-sleep { > + compatible = "arm,idle-state"; > + arm,psci-suspend-param = <0x10000>; > + entry-latency-us = <800>; > + exit-latency-us = <3200>; > + local-timer-stop; > + min-residency-us = <4200>; > + }; > + > + cluster_sleep: cluster-sleep { > + compatible = "arm,idle-state"; > + arm,psci-suspend-param = <0x1010000>; > + entry-latency-us = <1000>; > + exit-latency-us = <3200>; > + local-timer-stop; > + min-residency-us = <4500>; > + }; > + }; > + > + cpu-map { > + cluster0 { > + core0 { cpu = <&cpu0>; }; > + core1 { cpu = <&cpu1>; }; > + core2 { cpu = <&cpu2>; }; > + core3 { cpu = <&cpu3>; }; > + }; > + > + cluster1 { > + core0 { cpu = <&cpu4>; }; > + core1 { cpu = <&cpu5>; }; > + core2 { cpu = <&cpu6>; }; > + core3 { cpu = <&cpu7>; }; > + }; > + > + cluster2 { > + core0 { cpu = <&cpu8>; }; > + core1 { cpu = <&cpu9>; }; > + core2 { cpu = <&cpu10>; }; > + core3 { cpu = <&cpu11>; }; > + }; > + > + cluster3 { > + core0 { cpu = <&cpu12>; }; > + core1 { cpu = <&cpu13>; }; > + core2 { cpu = <&cpu14>; }; > + core3 { cpu = <&cpu15>; }; > + }; > + }; > + > + cpu0: cpu@0 { > + compatible = "arm,cortex-a720ae"; > + device_type = "cpu"; > + reg = <0x00 0x0000>; > + enable-method = "psci"; > + > + clocks = <&scmi_dvfs 0>; > + cpu-idle-states = <&cpu_sleep &cluster_sleep>; > + next-level-cache = <&cl0_l2_0>; > + > + i-cache-line-size = <64>; > + i-cache-sets = <256>; > + i-cache-size = <0x10000>; > + > + d-cache-line-size = <64>; > + d-cache-sets = <256>; > + d-cache-size = <0x10000>; > + > + cl0_l2_0: l2-cache { > + compatible = "cache"; > + cache-level = <2>; > + cache-line-size = <64>; > + cache-sets = <0x400>; /* 8-way set */ > + cache-size = <0x80000>; /* 512KB */ > + cache-unified; > + next-level-cache = <&cl0_l3>; > + }; > + }; > + > + cpu1: cpu@100 { > + compatible = "arm,cortex-a720ae"; > + device_type = "cpu"; > + reg = <0x00 0x0100>; > + enable-method = "psci"; > + > + clocks = <&scmi_dvfs 0>; > + cpu-idle-states = <&cpu_sleep &cluster_sleep>; > + next-level-cache = <&cl0_l2_1>; > + > + i-cache-line-size = <64>; > + i-cache-sets = <256>; > + i-cache-size = <0x10000>; > + > + d-cache-line-size = <64>; > + d-cache-sets = <256>; > + d-cache-size = <0x10000>; > + > + cl0_l2_1: l2-cache { > + compatible = "cache"; > + cache-level = <2>; > + cache-line-size = <64>; > + cache-sets = <0x400>; /* 8-way set */ > + cache-size = <0x80000>; /* 512KB */ > + cache-unified; > + next-level-cache = <&cl0_l3>; > + }; > + }; > + > + cpu2: cpu@200 { > + compatible = "arm,cortex-a720ae"; > + device_type = "cpu"; > + reg = <0x00 0x0200>; > + enable-method = "psci"; > + > + clocks = <&scmi_dvfs 0>; > + cpu-idle-states = <&cpu_sleep &cluster_sleep>; > + next-level-cache = <&cl0_l2_2>; > + > + i-cache-line-size = <64>; > + i-cache-sets = <256>; > + i-cache-size = <0x10000>; > + > + d-cache-line-size = <64>; > + d-cache-sets = <256>; > + d-cache-size = <0x10000>; > + > + cl0_l2_2: l2-cache { > + compatible = "cache"; > + cache-level = <2>; > + cache-line-size = <64>; > + cache-sets = <0x400>; /* 8-way set */ > + cache-size = <0x80000>; /* 512KB */ > + cache-unified; > + next-level-cache = <&cl0_l3>; > + }; > + }; > + > + cpu3: cpu@300 { > + compatible = "arm,cortex-a720ae"; > + device_type = "cpu"; > + reg = <0x00 0x0300>; > + enable-method = "psci"; > + > + clocks = <&scmi_dvfs 0>; > + cpu-idle-states = <&cpu_sleep &cluster_sleep>; > + next-level-cache = <&cl0_l2_3>; > + > + i-cache-line-size = <64>; > + i-cache-sets = <256>; > + i-cache-size = <0x10000>; > + > + d-cache-line-size = <64>; > + d-cache-sets = <256>; > + d-cache-size = <0x10000>; > + > + cl0_l2_3: l2-cache { > + compatible = "cache"; > + cache-level = <2>; > + cache-line-size = <64>; > + cache-sets = <0x400>; /* 8-way set */ > + cache-size = <0x80000>; /* 512KB */ > + cache-unified; > + next-level-cache = <&cl0_l3>; > + }; > + }; > + > + cpu4: cpu@10000 { > + compatible = "arm,cortex-a720ae"; > + device_type = "cpu"; > + reg = <0x00 0x10000>; > + enable-method = "psci"; > + > + clocks = <&scmi_dvfs 0>; > + cpu-idle-states = <&cpu_sleep &cluster_sleep>; > + next-level-cache = <&cl1_l2_0>; > + > + i-cache-line-size = <64>; > + i-cache-sets = <256>; > + i-cache-size = <0x10000>; > + > + d-cache-line-size = <64>; > + d-cache-sets = <256>; > + d-cache-size = <0x10000>; > + > + cl1_l2_0: l2-cache { > + compatible = "cache"; > + cache-level = <2>; > + cache-line-size = <64>; > + cache-sets = <0x400>; /* 8-way set */ > + cache-size = <0x80000>; /* 512KB */ > + cache-unified; > + next-level-cache = <&cl1_l3>; > + }; > + }; > + > + cpu5: cpu@10100 { > + compatible = "arm,cortex-a720ae"; > + device_type = "cpu"; > + reg = <0x00 0x10100>; > + enable-method = "psci"; > + > + clocks = <&scmi_dvfs 0>; > + cpu-idle-states = <&cpu_sleep &cluster_sleep>; > + next-level-cache = <&cl1_l2_1>; > + > + i-cache-line-size = <64>; > + i-cache-sets = <256>; > + i-cache-size = <0x10000>; > + > + d-cache-line-size = <64>; > + d-cache-sets = <256>; > + d-cache-size = <0x10000>; > + > + cl1_l2_1: l2-cache { > + compatible = "cache"; > + cache-level = <2>; > + cache-line-size = <64>; > + cache-sets = <0x400>; /* 8-way set */ > + cache-size = <0x80000>; /* 512KB */ > + cache-unified; > + next-level-cache = <&cl1_l3>; > + }; > + }; > + > + cpu6: cpu@10200 { > + compatible = "arm,cortex-a720ae"; > + device_type = "cpu"; > + reg = <0x00 0x10200>; > + enable-method = "psci"; > + > + clocks = <&scmi_dvfs 0>; > + cpu-idle-states = <&cpu_sleep &cluster_sleep>; > + next-level-cache = <&cl1_l2_2>; > + > + i-cache-line-size = <64>; > + i-cache-sets = <256>; > + i-cache-size = <0x10000>; > + > + d-cache-line-size = <64>; > + d-cache-sets = <256>; > + d-cache-size = <0x10000>; > + > + cl1_l2_2: l2-cache { > + compatible = "cache"; > + cache-level = <2>; > + cache-line-size = <64>; > + cache-sets = <0x400>; /* 8-way set */ > + cache-size = <0x80000>; /* 512KB */ > + cache-unified; > + next-level-cache = <&cl1_l3>; > + }; > + }; > + > + cpu7: cpu@10300 { > + compatible = "arm,cortex-a720ae"; > + device_type = "cpu"; > + reg = <0x00 0x10300>; > + enable-method = "psci"; > + > + clocks = <&scmi_dvfs 0>; > + cpu-idle-states = <&cpu_sleep &cluster_sleep>; > + next-level-cache = <&cl1_l2_3>; > + > + i-cache-line-size = <64>; > + i-cache-sets = <256>; > + i-cache-size = <0x10000>; > + > + d-cache-line-size = <64>; > + d-cache-sets = <256>; > + d-cache-size = <0x10000>; > + > + cl1_l2_3: l2-cache { > + compatible = "cache"; > + cache-level = <2>; > + cache-line-size = <64>; > + cache-sets = <0x400>; /* 8-way set */ > + cache-size = <0x80000>; /* 512KB */ > + cache-unified; > + next-level-cache = <&cl1_l3>; > + }; > + }; > + > + cpu8: cpu@20000 { > + compatible = "arm,cortex-a720ae"; > + device_type = "cpu"; > + reg = <0x00 0x20000>; > + enable-method = "psci"; > + > + clocks = <&scmi_dvfs 0>; > + cpu-idle-states = <&cpu_sleep &cluster_sleep>; > + next-level-cache = <&cl2_l2_0>; > + > + i-cache-line-size = <64>; > + i-cache-sets = <256>; > + i-cache-size = <0x10000>; > + > + d-cache-line-size = <64>; > + d-cache-sets = <256>; > + d-cache-size = <0x10000>; > + > + cl2_l2_0: l2-cache { > + compatible = "cache"; > + cache-level = <2>; > + cache-line-size = <64>; > + cache-sets = <0x400>; /* 8-way set */ > + cache-size = <0x80000>; /* 512KB */ > + cache-unified; > + next-level-cache = <&cl2_l3>; > + }; > + }; > + > + cpu9: cpu@20100 { > + compatible = "arm,cortex-a720ae"; > + device_type = "cpu"; > + reg = <0x00 0x20100>; > + enable-method = "psci"; > + > + clocks = <&scmi_dvfs 0>; > + cpu-idle-states = <&cpu_sleep &cluster_sleep>; > + next-level-cache = <&cl2_l2_1>; > + > + i-cache-line-size = <64>; > + i-cache-sets = <256>; > + i-cache-size = <0x10000>; > + > + d-cache-line-size = <64>; > + d-cache-sets = <256>; > + d-cache-size = <0x10000>; > + > + cl2_l2_1: l2-cache { > + compatible = "cache"; > + cache-level = <2>; > + cache-line-size = <64>; > + cache-sets = <0x400>; /* 8-way set */ > + cache-size = <0x80000>; /* 512KB */ > + cache-unified; > + next-level-cache = <&cl2_l3>; > + }; > + }; > + > + cpu10: cpu@20200 { > + compatible = "arm,cortex-a720ae"; > + device_type = "cpu"; > + reg = <0x00 0x20200>; > + enable-method = "psci"; > + > + clocks = <&scmi_dvfs 0>; > + cpu-idle-states = <&cpu_sleep &cluster_sleep>; > + next-level-cache = <&cl2_l2_2>; > + > + i-cache-line-size = <64>; > + i-cache-sets = <256>; > + i-cache-size = <0x10000>; > + > + d-cache-line-size = <64>; > + d-cache-sets = <256>; > + d-cache-size = <0x10000>; > + > + cl2_l2_2: l2-cache { > + compatible = "cache"; > + cache-level = <2>; > + cache-line-size = <64>; > + cache-sets = <0x400>; /* 8-way set */ > + cache-size = <0x80000>; /* 512KB */ > + cache-unified; > + next-level-cache = <&cl2_l3>; > + }; > + }; > + > + cpu11: cpu@20300 { > + compatible = "arm,cortex-a720ae"; > + device_type = "cpu"; > + reg = <0x00 0x20300>; > + enable-method = "psci"; > + > + clocks = <&scmi_dvfs 0>; > + cpu-idle-states = <&cpu_sleep &cluster_sleep>; > + next-level-cache = <&cl2_l2_3>; > + > + i-cache-line-size = <64>; > + i-cache-sets = <256>; > + i-cache-size = <0x10000>; > + > + d-cache-line-size = <64>; > + d-cache-sets = <256>; > + d-cache-size = <0x10000>; > + > + cl2_l2_3: l2-cache { > + compatible = "cache"; > + cache-level = <2>; > + cache-line-size = <64>; > + cache-sets = <0x400>; /* 8-way set */ > + cache-size = <0x80000>; /* 512KB */ > + cache-unified; > + next-level-cache = <&cl2_l3>; > + }; > + }; > + > + cpu12: cpu@30000 { > + compatible = "arm,cortex-a720ae"; > + device_type = "cpu"; > + reg = <0x00 0x30000>; > + enable-method = "psci"; > + > + clocks = <&scmi_dvfs 0>; > + cpu-idle-states = <&cpu_sleep &cluster_sleep>; > + next-level-cache = <&cl3_l2_0>; > + > + i-cache-line-size = <64>; > + i-cache-sets = <256>; > + i-cache-size = <0x10000>; > + > + d-cache-line-size = <64>; > + d-cache-sets = <256>; > + d-cache-size = <0x10000>; > + > + cl3_l2_0: l2-cache { > + compatible = "cache"; > + cache-level = <2>; > + cache-line-size = <64>; > + cache-sets = <0x400>; /* 8-way set */ > + cache-size = <0x80000>; /* 512KB */ > + cache-unified; > + next-level-cache = <&cl3_l3>; > + }; > + }; > + > + cpu13: cpu@30100 { > + compatible = "arm,cortex-a720ae"; > + device_type = "cpu"; > + reg = <0x00 0x30100>; > + enable-method = "psci"; > + > + clocks = <&scmi_dvfs 0>; > + cpu-idle-states = <&cpu_sleep &cluster_sleep>; > + next-level-cache = <&cl3_l2_1>; > + > + i-cache-line-size = <64>; > + i-cache-sets = <256>; > + i-cache-size = <0x10000>; > + > + d-cache-line-size = <64>; > + d-cache-sets = <256>; > + d-cache-size = <0x10000>; > + > + cl3_l2_1: l2-cache { > + compatible = "cache"; > + cache-level = <2>; > + cache-line-size = <64>; > + cache-sets = <0x400>; /* 8-way set */ > + cache-size = <0x80000>; /* 512KB */ > + cache-unified; > + next-level-cache = <&cl3_l3>; > + }; > + }; > + > + cpu14: cpu@30200 { > + compatible = "arm,cortex-a720ae"; > + device_type = "cpu"; > + reg = <0x00 0x30200>; > + enable-method = "psci"; > + > + clocks = <&scmi_dvfs 0>; > + cpu-idle-states = <&cpu_sleep &cluster_sleep>; > + next-level-cache = <&cl3_l2_2>; > + > + i-cache-line-size = <64>; > + i-cache-sets = <256>; > + i-cache-size = <0x10000>; > + > + d-cache-line-size = <64>; > + d-cache-sets = <256>; > + d-cache-size = <0x10000>; > + > + cl3_l2_2: l2-cache { > + compatible = "cache"; > + cache-level = <2>; > + cache-line-size = <64>; > + cache-sets = <0x400>; /* 8-way set */ > + cache-size = <0x80000>; /* 512KB */ > + cache-unified; > + next-level-cache = <&cl3_l3>; > + }; > + }; > + > + cpu15: cpu@30300 { > + compatible = "arm,cortex-a720ae"; > + device_type = "cpu"; > + reg = <0x00 0x30300>; > + enable-method = "psci"; > + > + clocks = <&scmi_dvfs 0>; > + cpu-idle-states = <&cpu_sleep &cluster_sleep>; > + next-level-cache = <&cl3_l2_3>; > + > + i-cache-line-size = <64>; > + i-cache-sets = <256>; > + i-cache-size = <0x10000>; > + > + d-cache-line-size = <64>; > + d-cache-sets = <256>; > + d-cache-size = <0x10000>; > + > + cl3_l2_3: l2-cache { > + compatible = "cache"; > + cache-level = <2>; > + cache-line-size = <64>; > + cache-sets = <0x400>; /* 8-way set */ > + cache-size = <0x80000>; /* 512KB */ > + cache-unified; > + next-level-cache = <&cl3_l3>; > + }; > + }; > + > + cl0_l3: l3-cache0 { > + compatible = "cache"; > + cache-level = <3>; > + cache-line-size = <64>; > + cache-sets = <0x1000>; /* 16-way set */ > + cache-size = <0x400000>; /* 4MB */ > + cache-unified; > + }; > + > + cl1_l3: l3-cache1 { > + compatible = "cache"; > + cache-level = <3>; > + cache-line-size = <64>; > + cache-sets = <0x1000>; /* 16-way set */ > + cache-size = <0x400000>; /* 4MB */ > + cache-unified; > + }; > + > + cl2_l3: l3-cache2 { > + compatible = "cache"; > + cache-level = <3>; > + cache-line-size = <64>; > + cache-sets = <0x1000>; /* 16-way set */ > + cache-size = <0x400000>; /* 4MB */ > + cache-unified; > + }; > + > + cl3_l3: l3-cache3 { > + compatible = "cache"; > + cache-level = <3>; > + cache-line-size = <64>; > + cache-sets = <0x1000>; /* 16-way set */ > + cache-size = <0x400000>; /* 4MB */ > + cache-unified; > + }; > + }; > + > + firmware { > + scmi { > + compatible = "arm,scmi"; > + #address-cells = <1>; > + #size-cells = <0>; > + > + mbox-names = "tx", "tx_reply", "rx"; > + mboxes = <&mbox_db_tx 0 0 0>, > + <&mbox_db_rx 0 0 0>, > + <&mbox_db_rx 0 0 2>; > + shmem = <&scmi_shmem_tx &scmi_shmem_rx>; > + > + scmi_dvfs: protocol@13 { > + reg = <0x13>; > + #clock-cells = <1>; > + }; > + }; > + }; > + > + dsu-pmu-0 { > + compatible = "arm,dsu-pmu"; > + cpus = <&cpu0 &cpu1 &cpu2 &cpu3>; > + interrupts = ; > + }; > + > + dsu-pmu-1 { > + compatible = "arm,dsu-pmu"; > + cpus = <&cpu4 &cpu5 &cpu6 &cpu7>; > + interrupts = ; > + }; > + > + dsu-pmu-2 { > + compatible = "arm,dsu-pmu"; > + cpus = <&cpu8 &cpu9 &cpu10 &cpu11>; > + interrupts = ; > + }; > + > + dsu-pmu-3 { > + compatible = "arm,dsu-pmu"; > + cpus = <&cpu12 &cpu13 &cpu14 &cpu15>; > + interrupts = ; > + }; > + > + psci { > + compatible = "arm,psci-1.0", "arm,psci-0.2"; > + method = "smc"; > + }; > + > + soc: soc { > + compatible = "simple-bus"; > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + > + timer@1a810000 { > + compatible = "arm,armv7-timer-mem"; > + reg = <0x0 0x1a810000 0x0 0x10000>; > + #address-cells = <1>; > + #size-cells = <1>; > + > + /* > + * Map child space [0x0..0x30000) to parent @ 0x1a810000 > + */ > + ranges = <0x0 0x0 0x1a810000 0x00030000>; > + > + frame@20000 { > + reg = <0x20000 0x10000>; > + frame-number = <0>; > + interrupts = ; > + }; > + }; > + > + gic: interrupt-controller@20800000 { > + compatible = "arm,gic-v3"; > + #interrupt-cells = <3>; > + #address-cells = <2>; > + #size-cells = <2>; > + #redistributor-regions = <16>; > + interrupt-controller; > + interrupts = ; > + ranges; > + > + /* > + * With GIC-A720AE multiview enabled, GICR_TYPER.Last is > + * always reported as 1 on redistributor views other than > + * view 0. This breaks discovery of a single contiguous > + * GICR frame region, so each core is described with its own > + * redistributor region. > + */ > + reg = <0x0 0x20800000 0x0 0x10000>, /* GICD */ > + <0x0 0x20880000 0x0 0x40000>, /* 16 * GICR */ > + <0x0 0x208c0000 0x0 0x40000>, > + <0x0 0x20900000 0x0 0x40000>, > + <0x0 0x20940000 0x0 0x40000>, > + <0x0 0x20980000 0x0 0x40000>, > + <0x0 0x209c0000 0x0 0x40000>, > + <0x0 0x20a00000 0x0 0x40000>, > + <0x0 0x20a40000 0x0 0x40000>, > + <0x0 0x20a80000 0x0 0x40000>, > + <0x0 0x20ac0000 0x0 0x40000>, > + <0x0 0x20b00000 0x0 0x40000>, > + <0x0 0x20b40000 0x0 0x40000>, > + <0x0 0x20b80000 0x0 0x40000>, > + <0x0 0x20bc0000 0x0 0x40000>, > + <0x0 0x20c00000 0x0 0x40000>, > + <0x0 0x20c40000 0x0 0x40000>; > + > + its: msi-controller@20840000 { > + compatible = "arm,gic-v3-its"; > + reg = <0x0 0x20840000 0x0 0x40000>; > + msi-controller; > + #msi-cells = <1>; > + }; > + }; > + > + /* > + * UART is fixed at 24MHz, both UARTCLK and PCLK. > + */ > + soc_serial0: serial@1a400000 { > + compatible = "arm,pl011", "arm,primecell"; > + reg = <0x0 0x1a400000 0x0 0x10000>; > + interrupts = ; > + clocks = <&soc_clk24mhz>, <&soc_clk24mhz>; > + clock-names = "uartclk", "apb_pclk"; > + }; > + > + watchdog@1a420000 { > + compatible = "arm,sbsa-gwdt"; > + reg = <0x0 0x1a420000 0x0 0x10000>, > + <0x0 0x1a430000 0x0 0x10000>; > + interrupts = ; > + }; > + > + rtc@300d0000 { > + compatible = "arm,pl031", "arm,primecell"; > + reg = <0x0 0x300d0000 0x0 0x10000>; > + interrupts = ; > + clocks = <&soc_clk24mhz>; > + clock-names = "apb_pclk"; > + }; > + > + mbox_db_tx: mailbox@40020000 { > + compatible = "arm,mhuv3"; > + reg = <0x0 0x40020000 0x0 0x30000>; > + interrupts = ; > + interrupt-names = "combined"; > + clocks = <&soc_clk24mhz>; > + #mbox-cells = <3>; > + }; > + > + mbox_db_rx: mailbox@40060000 { > + compatible = "arm,mhuv3"; > + reg = <0x0 0x40060000 0x0 0x30000>; > + interrupts = ; > + interrupt-names = "combined"; > + clocks = <&soc_clk24mhz>; > + #mbox-cells = <3>; > + }; > + }; > + > + timer { > + compatible = "arm,armv8-timer"; > + interrupts = , > + , > + , > + , > + ; > + }; > + > + sram: sram@104000 { > + compatible = "mmio-sram"; > + reg = <0x0 0x00104000 0x0 0x00001000>; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0 0x0 0x00104000 0x00001000>; > + > + scmi_shmem_tx: scpshmem-sram-section@0 { > + compatible = "arm,scmi-shmem"; > + reg = <0x0 0x100>; > + }; > + > + scmi_shmem_rx: scpshmem-sram-section@100 { > + compatible = "arm,scmi-shmem"; > + reg = <0x100 0x100>; > + }; > + }; > + > + memory@80000000 { > + device_type = "memory"; > + > + /* ~2GB mapped at 2GB, another 2GB at 2TB */ > + reg = <0x00000000 0x80000000 0x00000000 0x7f000000>, > + <0x00000200 0x00000000 0x00000000 0x80000000>; > + }; > +}; >