From: f.fainelli@gmail.com (Florian Fainelli)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v3 1/6] arm: Add BTB invalidation on switch_mm for Cortex-A9, A12 and A17
Date: Fri, 26 Jan 2018 12:44:16 -0800 [thread overview]
Message-ID: <1e81134a-c88f-1764-a193-24e55eb43819@gmail.com> (raw)
In-Reply-To: <20180125152139.32431-2-marc.zyngier@arm.com>
On 01/25/2018 07:21 AM, Marc Zyngier wrote:
> In order to avoid aliasing attacks against the branch predictor,
> some implementations require to invalidate the BTB when switching
> from one user context to another.
>
> For this, we reuse the existing implementation for Cortex-A8, and
> apply it to A9, A12 and A17.
Should this read: and apply it to A8, A9, A12 and A17
>
> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
> ---
> arch/arm/mm/proc-v7-2level.S | 4 ++--
> arch/arm/mm/proc-v7-3level.S | 6 ++++++
> arch/arm/mm/proc-v7.S | 30 +++++++++++++++---------------
> 3 files changed, 23 insertions(+), 17 deletions(-)
>
> diff --git a/arch/arm/mm/proc-v7-2level.S b/arch/arm/mm/proc-v7-2level.S
> index c6141a5435c3..0422e58b74e8 100644
> --- a/arch/arm/mm/proc-v7-2level.S
> +++ b/arch/arm/mm/proc-v7-2level.S
> @@ -41,7 +41,7 @@
> * even on Cortex-A8 revisions not affected by 430973.
> * If IBE is not set, the flush BTAC/BTB won't do anything.
> */
> -ENTRY(cpu_ca8_switch_mm)
> +ENTRY(cpu_v7_btbinv_switch_mm)
> #ifdef CONFIG_MMU
> mov r2, #0
> mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB
> @@ -66,7 +66,7 @@ ENTRY(cpu_v7_switch_mm)
> #endif
> bx lr
> ENDPROC(cpu_v7_switch_mm)
> -ENDPROC(cpu_ca8_switch_mm)
> +ENDPROC(cpu_v7_btbinv_switch_mm)
>
> /*
> * cpu_v7_set_pte_ext(ptep, pte)
> diff --git a/arch/arm/mm/proc-v7-3level.S b/arch/arm/mm/proc-v7-3level.S
> index 7d16bbc4102b..934272e1fa08 100644
> --- a/arch/arm/mm/proc-v7-3level.S
> +++ b/arch/arm/mm/proc-v7-3level.S
> @@ -54,6 +54,11 @@
> * Set the translation table base pointer to be pgd_phys (physical address of
> * the new TTB).
> */
> +ENTRY(cpu_v7_btbinv_switch_mm)
> +#ifdef CONFIG_MMU
> + mov r2, #0
> + mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB
> +#endif
> ENTRY(cpu_v7_switch_mm)
> #ifdef CONFIG_MMU
> mmid r2, r2
> @@ -64,6 +69,7 @@ ENTRY(cpu_v7_switch_mm)
> #endif
> ret lr
> ENDPROC(cpu_v7_switch_mm)
> +ENDPROC(cpu_v7_btbinv_switch_mm)
>
> #ifdef __ARMEB__
> #define rl r3
> diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
> index 01d64c0b2563..0a14967fd400 100644
> --- a/arch/arm/mm/proc-v7.S
> +++ b/arch/arm/mm/proc-v7.S
> @@ -159,18 +159,18 @@ ENDPROC(cpu_v7_do_resume)
> #endif
>
> /*
> - * Cortex-A8
> + * Cortex-A8/A12/A17 that require a BTB invalidation on switch_mm
Should this read Cortex-A8/A9/A12/A17?
--
Florian
next prev parent reply other threads:[~2018-01-26 20:44 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-01-25 15:21 [PATCH v3 0/6] 32bit ARM branch predictor hardening Marc Zyngier
2018-01-25 15:21 ` [PATCH v3 1/6] arm: Add BTB invalidation on switch_mm for Cortex-A9, A12 and A17 Marc Zyngier
2018-01-26 20:44 ` Florian Fainelli [this message]
2018-01-30 17:27 ` Marc Zyngier
2018-01-25 15:21 ` [PATCH v3 2/6] arm: Invalidate BTB on prefetch abort outside of user mapping on Cortex A8, A9, " Marc Zyngier
2018-01-31 2:13 ` Fabio Estevam
2018-01-25 15:21 ` [PATCH v3 3/6] arm: KVM: Invalidate BTB on guest exit for Cortex-A12/A17 Marc Zyngier
2018-01-26 9:23 ` Christoffer Dall
2018-01-26 17:12 ` Robin Murphy
2018-01-31 12:11 ` Marc Zyngier
2018-01-31 14:25 ` Robin Murphy
2018-01-25 15:21 ` [PATCH v3 4/6] arm: Add icache invalidation on switch_mm for Cortex-A15 Marc Zyngier
2018-01-26 9:14 ` Christoffer Dall
2018-01-26 9:30 ` Marc Zyngier
2018-01-26 16:20 ` Florian Fainelli
2018-01-26 16:33 ` Marc Zyngier
2018-01-26 17:20 ` Robin Murphy
2018-01-27 22:23 ` Florian Fainelli
2018-01-28 11:55 ` Marc Zyngier
2018-01-29 18:05 ` Florian Fainelli
2018-01-29 18:13 ` Marc Zyngier
2018-01-25 15:21 ` [PATCH v3 5/6] arm: Invalidate icache on prefetch abort outside of user mapping on Cortex-A15 Marc Zyngier
2018-01-25 15:21 ` [PATCH v3 6/6] arm: KVM: Invalidate icache on guest exit for Cortex-A15 Marc Zyngier
2018-01-26 9:30 ` [PATCH v3 0/6] 32bit ARM branch predictor hardening Christoffer Dall
2018-01-26 16:39 ` Andre Przywara
2018-01-29 11:36 ` Hanjun Guo
2018-01-29 14:58 ` Nishanth Menon
2018-01-31 12:45 ` Hanjun Guo
2018-01-31 18:53 ` Florian Fainelli
2018-01-31 19:07 ` Marc Zyngier
2018-01-31 19:54 ` André Przywara
2018-01-31 20:37 ` Florian Fainelli
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