* [PATCH v2 0/3] Enable smmu support on sdm845
@ 2018-08-14 10:27 Vivek Gautam
2018-08-14 10:27 ` [PATCH v2 1/3] dt-bindings: arm-smmu: Add binding doc for Qcom smmu-500 Vivek Gautam
` (2 more replies)
0 siblings, 3 replies; 9+ messages in thread
From: Vivek Gautam @ 2018-08-14 10:27 UTC (permalink / raw)
To: linux-arm-kernel
This series enables apps-smmu (arm,mmu-500) and gpu-smmu (qcom,smmu-v2)
on sdm845. gpu-smmu needs one power domain from gpu clock controller
whose driver was sent by Amit [1].
Changes since v1:
- Addressed Rob's review comments by adding a SoC specific compatible.
Have added a new dt-bindings patch for this.
- Updated node name to 'iommu'.
- Addressed Doug's review comment about removing status property from
smmu's nodes, as smmu is either present on the soc or not. Enabling
it is not a board-level decision.
[1] https://lore.kernel.org/patchwork/patch/973839/
Vivek Gautam (3):
dt-bindings: arm-smmu: Add binding doc for Qcom smmu-500
dts: arm64/sdm845: Add node for arm,mmu-500
dts: arm64/sdm845: Add node for qcom,smmu-v2
.../devicetree/bindings/iommu/arm,smmu.txt | 5 ++
arch/arm64/boot/dts/qcom/sdm845.dtsi | 95 ++++++++++++++++++++++
2 files changed, 100 insertions(+)
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply [flat|nested] 9+ messages in thread* [PATCH v2 1/3] dt-bindings: arm-smmu: Add binding doc for Qcom smmu-500 2018-08-14 10:27 [PATCH v2 0/3] Enable smmu support on sdm845 Vivek Gautam @ 2018-08-14 10:27 ` Vivek Gautam 2018-08-14 10:27 ` [PATCH v2 2/3] dts: arm64/sdm845: Add node for arm,mmu-500 Vivek Gautam 2018-08-14 10:27 ` [PATCH v2 3/3] dts: arm64/sdm845: Add node for qcom,smmu-v2 Vivek Gautam 2 siblings, 0 replies; 9+ messages in thread From: Vivek Gautam @ 2018-08-14 10:27 UTC (permalink / raw) To: linux-arm-kernel Qcom's implementation of arm,mmu-500 works well with current arm-smmu driver implementation. Adding a soc specific compatible along with arm,mmu-500 makes the bindings future safe. Signed-off-by: Vivek Gautam <vivek.gautam@codeaurora.org> --- Documentation/devicetree/bindings/iommu/arm,smmu.txt | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.txt b/Documentation/devicetree/bindings/iommu/arm,smmu.txt index 7c71a6ed465a..7d73b2a259fc 100644 --- a/Documentation/devicetree/bindings/iommu/arm,smmu.txt +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.txt @@ -18,6 +18,7 @@ conditions. "arm,mmu-500" "cavium,smmu-v2" "qcom,<soc>-smmu-v2", "qcom,smmu-v2" + "qcom,<soc>-smmu-500", "arm,mmu-500" depending on the particular implementation and/or the version of the architecture implemented. @@ -30,6 +31,10 @@ conditions. An example string would be - "qcom,msm8996-smmu-v2", "qcom,smmu-v2". + "qcom,<soc>-smmu-500" compatible string represents qcom's soc + specific implementation of arm,mmu-500, and should be present + along with "arm,mmu-500". + - reg : Base address and size of the SMMU. - #global-interrupts : The number of global interrupts exposed by the -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation ^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH v2 2/3] dts: arm64/sdm845: Add node for arm,mmu-500 2018-08-14 10:27 [PATCH v2 0/3] Enable smmu support on sdm845 Vivek Gautam 2018-08-14 10:27 ` [PATCH v2 1/3] dt-bindings: arm-smmu: Add binding doc for Qcom smmu-500 Vivek Gautam @ 2018-08-14 10:27 ` Vivek Gautam 2018-08-14 10:27 ` [PATCH v2 3/3] dts: arm64/sdm845: Add node for qcom,smmu-v2 Vivek Gautam 2 siblings, 0 replies; 9+ messages in thread From: Vivek Gautam @ 2018-08-14 10:27 UTC (permalink / raw) To: linux-arm-kernel Add device node for arm,mmu-500 available on sdm845. This MMU-500 with single TCU and multiple TBU architecture is shared among all the peripherals except gpu on sdm845. Signed-off-by: Vivek Gautam <vivek.gautam@codeaurora.org> --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 72 ++++++++++++++++++++++++++++++++++++ 1 file changed, 72 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index eb4ab33bf6f4..1c2be2082f33 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -989,6 +989,78 @@ cell-index = <0>; }; + apps_smmu: iommu at 15000000 { + compatible = "qcom,sdm845-smmu-500", "arm,mmu-500"; + reg = <0x15000000 0x80000>; + #iommu-cells = <2>; + #global-interrupts = <1>; + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>; + }; + apss_shared: mailbox at 17990000 { compatible = "qcom,sdm845-apss-shared"; reg = <0x17990000 0x1000>; -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation ^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH v2 3/3] dts: arm64/sdm845: Add node for qcom,smmu-v2 2018-08-14 10:27 [PATCH v2 0/3] Enable smmu support on sdm845 Vivek Gautam 2018-08-14 10:27 ` [PATCH v2 1/3] dt-bindings: arm-smmu: Add binding doc for Qcom smmu-500 Vivek Gautam 2018-08-14 10:27 ` [PATCH v2 2/3] dts: arm64/sdm845: Add node for arm,mmu-500 Vivek Gautam @ 2018-08-14 10:27 ` Vivek Gautam 2018-08-14 10:49 ` Robin Murphy 2 siblings, 1 reply; 9+ messages in thread From: Vivek Gautam @ 2018-08-14 10:27 UTC (permalink / raw) To: linux-arm-kernel Add device node for qcom,smmu-v2 available on sdm845. This smmu is available only to GPU device. Signed-off-by: Vivek Gautam <vivek.gautam@codeaurora.org> --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 1c2be2082f33..bd1ec5fa5146 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -6,6 +6,7 @@ */ #include <dt-bindings/clock/qcom,gcc-sdm845.h> +#include <dt-bindings/clock/qcom,gpucc-sdm845.h> #include <dt-bindings/clock/qcom,rpmh.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/soc/qcom,rpmh-rsc.h> @@ -989,6 +990,28 @@ cell-index = <0>; }; + gpu_smmu: iommu at 5040000 { + compatible = "qcom,sdm845-smmu-v2", "qcom,smmu-v2"; + reg = <0x5040000 0x10000>; + #iommu-cells = <1>; + #global-interrupts = <2>; + interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 370 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 371 IRQ_TYPE_EDGE_RISING>; + clock-names = "bus", "iface"; + clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gcc GCC_GPU_CFG_AHB_CLK>; + + /*power-domains = <&gpucc GPU_CX_GDSC>;*/ + }; + apps_smmu: iommu at 15000000 { compatible = "qcom,sdm845-smmu-500", "arm,mmu-500"; reg = <0x15000000 0x80000>; -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation ^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH v2 3/3] dts: arm64/sdm845: Add node for qcom,smmu-v2 2018-08-14 10:27 ` [PATCH v2 3/3] dts: arm64/sdm845: Add node for qcom,smmu-v2 Vivek Gautam @ 2018-08-14 10:49 ` Robin Murphy 2018-08-14 19:39 ` Vivek Gautam 0 siblings, 1 reply; 9+ messages in thread From: Robin Murphy @ 2018-08-14 10:49 UTC (permalink / raw) To: linux-arm-kernel Hi Vivek, On 14/08/18 11:27, Vivek Gautam wrote: > Add device node for qcom,smmu-v2 available on sdm845. > This smmu is available only to GPU device. > > Signed-off-by: Vivek Gautam <vivek.gautam@codeaurora.org> > --- > arch/arm64/boot/dts/qcom/sdm845.dtsi | 23 +++++++++++++++++++++++ > 1 file changed, 23 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi > index 1c2be2082f33..bd1ec5fa5146 100644 > --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi > +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi > @@ -6,6 +6,7 @@ > */ > > #include <dt-bindings/clock/qcom,gcc-sdm845.h> > +#include <dt-bindings/clock/qcom,gpucc-sdm845.h> > #include <dt-bindings/clock/qcom,rpmh.h> > #include <dt-bindings/interrupt-controller/arm-gic.h> > #include <dt-bindings/soc/qcom,rpmh-rsc.h> > @@ -989,6 +990,28 @@ > cell-index = <0>; > }; > > + gpu_smmu: iommu at 5040000 { > + compatible = "qcom,sdm845-smmu-v2", "qcom,smmu-v2"; Which of "sdm845" or "msm8996"[1] is the actual SoC name here? Robin. [1] https://www.mail-archive.com/freedreno at lists.freedesktop.org/msg02659.html > + reg = <0x5040000 0x10000>; > + #iommu-cells = <1>; > + #global-interrupts = <2>; > + interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>, > + <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>, > + <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>, > + <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>, > + <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>, > + <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>, > + <GIC_SPI 370 IRQ_TYPE_EDGE_RISING>, > + <GIC_SPI 371 IRQ_TYPE_EDGE_RISING>; > + clock-names = "bus", "iface"; > + clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, > + <&gcc GCC_GPU_CFG_AHB_CLK>; > + > + /*power-domains = <&gpucc GPU_CX_GDSC>;*/ > + }; > + > apps_smmu: iommu at 15000000 { > compatible = "qcom,sdm845-smmu-500", "arm,mmu-500"; > reg = <0x15000000 0x80000>; > ^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v2 3/3] dts: arm64/sdm845: Add node for qcom,smmu-v2 2018-08-14 10:49 ` Robin Murphy @ 2018-08-14 19:39 ` Vivek Gautam 2018-08-14 22:57 ` Rob Herring 0 siblings, 1 reply; 9+ messages in thread From: Vivek Gautam @ 2018-08-14 19:39 UTC (permalink / raw) To: linux-arm-kernel Adding Jordan here. On Tue, Aug 14, 2018 at 4:19 PM, Robin Murphy <robin.murphy@arm.com> wrote: > Hi Vivek, > > On 14/08/18 11:27, Vivek Gautam wrote: >> >> Add device node for qcom,smmu-v2 available on sdm845. >> This smmu is available only to GPU device. >> >> Signed-off-by: Vivek Gautam <vivek.gautam@codeaurora.org> >> --- >> arch/arm64/boot/dts/qcom/sdm845.dtsi | 23 +++++++++++++++++++++++ >> 1 file changed, 23 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi >> b/arch/arm64/boot/dts/qcom/sdm845.dtsi >> index 1c2be2082f33..bd1ec5fa5146 100644 >> --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi >> +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi >> @@ -6,6 +6,7 @@ >> */ >> #include <dt-bindings/clock/qcom,gcc-sdm845.h> >> +#include <dt-bindings/clock/qcom,gpucc-sdm845.h> >> #include <dt-bindings/clock/qcom,rpmh.h> >> #include <dt-bindings/interrupt-controller/arm-gic.h> >> #include <dt-bindings/soc/qcom,rpmh-rsc.h> >> @@ -989,6 +990,28 @@ >> cell-index = <0>; >> }; >> + gpu_smmu: iommu at 5040000 { >> + compatible = "qcom,sdm845-smmu-v2", >> "qcom,smmu-v2"; > > > Which of "sdm845" or "msm8996"[1] is the actual SoC name here? Well, the bindings use the SoC prefix with smmu-v2, so it should be sdm845 for this SoC. This is same as I posted in my v1 of the series [2]. Using 8996 based string in sdm845 makes things look awful. Thanks Vivek [2] https://patchwork.kernel.org/patch/10534989/ > > Robin. > > [1] > https://www.mail-archive.com/freedreno at lists.freedesktop.org/msg02659.html > >> + reg = <0x5040000 0x10000>; >> + #iommu-cells = <1>; >> + #global-interrupts = <2>; >> + interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>, >> + <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>, >> + <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>, >> + <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>, >> + <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>, >> + <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>, >> + <GIC_SPI 370 IRQ_TYPE_EDGE_RISING>, >> + <GIC_SPI 371 IRQ_TYPE_EDGE_RISING>; >> + clock-names = "bus", "iface"; >> + clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, >> + <&gcc GCC_GPU_CFG_AHB_CLK>; >> + >> + /*power-domains = <&gpucc GPU_CX_GDSC>;*/ >> + }; >> + >> apps_smmu: iommu at 15000000 { >> compatible = "qcom,sdm845-smmu-500", >> "arm,mmu-500"; >> reg = <0x15000000 0x80000>; >> > _______________________________________________ > iommu mailing list > iommu at lists.linux-foundation.org > https://lists.linuxfoundation.org/mailman/listinfo/iommu -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation ^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v2 3/3] dts: arm64/sdm845: Add node for qcom,smmu-v2 2018-08-14 19:39 ` Vivek Gautam @ 2018-08-14 22:57 ` Rob Herring 2018-08-27 8:56 ` Vivek Gautam 0 siblings, 1 reply; 9+ messages in thread From: Rob Herring @ 2018-08-14 22:57 UTC (permalink / raw) To: linux-arm-kernel On Wed, Aug 15, 2018 at 01:09:43AM +0530, Vivek Gautam wrote: > Adding Jordan here. > > On Tue, Aug 14, 2018 at 4:19 PM, Robin Murphy <robin.murphy@arm.com> wrote: > > Hi Vivek, > > > > On 14/08/18 11:27, Vivek Gautam wrote: > >> > >> Add device node for qcom,smmu-v2 available on sdm845. > >> This smmu is available only to GPU device. > >> > >> Signed-off-by: Vivek Gautam <vivek.gautam@codeaurora.org> > >> --- > >> arch/arm64/boot/dts/qcom/sdm845.dtsi | 23 +++++++++++++++++++++++ > >> 1 file changed, 23 insertions(+) > >> > >> diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi > >> b/arch/arm64/boot/dts/qcom/sdm845.dtsi > >> index 1c2be2082f33..bd1ec5fa5146 100644 > >> --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi > >> +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi > >> @@ -6,6 +6,7 @@ > >> */ > >> #include <dt-bindings/clock/qcom,gcc-sdm845.h> > >> +#include <dt-bindings/clock/qcom,gpucc-sdm845.h> > >> #include <dt-bindings/clock/qcom,rpmh.h> > >> #include <dt-bindings/interrupt-controller/arm-gic.h> > >> #include <dt-bindings/soc/qcom,rpmh-rsc.h> > >> @@ -989,6 +990,28 @@ > >> cell-index = <0>; > >> }; > >> + gpu_smmu: iommu at 5040000 { > >> + compatible = "qcom,sdm845-smmu-v2", > >> "qcom,smmu-v2"; > > > > > > Which of "sdm845" or "msm8996"[1] is the actual SoC name here? > > Well, the bindings use the SoC prefix with smmu-v2, so it should be > sdm845 for this SoC. This is same as I posted in my v1 of the series [2]. > Using 8996 based string in sdm845 makes things look awful. You need to list valid values of '<soc>' in the binding. Otherwise we get this confusion. Rob ^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v2 3/3] dts: arm64/sdm845: Add node for qcom,smmu-v2 2018-08-14 22:57 ` Rob Herring @ 2018-08-27 8:56 ` Vivek Gautam 2018-08-27 11:12 ` Vivek Gautam 0 siblings, 1 reply; 9+ messages in thread From: Vivek Gautam @ 2018-08-27 8:56 UTC (permalink / raw) To: linux-arm-kernel Hi Rob, Robin, On 8/15/2018 4:27 AM, Rob Herring wrote: > On Wed, Aug 15, 2018 at 01:09:43AM +0530, Vivek Gautam wrote: >> Adding Jordan here. >> >> On Tue, Aug 14, 2018 at 4:19 PM, Robin Murphy <robin.murphy@arm.com> wrote: >>> Hi Vivek, >>> >>> On 14/08/18 11:27, Vivek Gautam wrote: >>>> Add device node for qcom,smmu-v2 available on sdm845. >>>> This smmu is available only to GPU device. >>>> >>>> Signed-off-by: Vivek Gautam <vivek.gautam@codeaurora.org> >>>> --- >>>> arch/arm64/boot/dts/qcom/sdm845.dtsi | 23 +++++++++++++++++++++++ >>>> 1 file changed, 23 insertions(+) >>>> >>>> diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi >>>> b/arch/arm64/boot/dts/qcom/sdm845.dtsi >>>> index 1c2be2082f33..bd1ec5fa5146 100644 >>>> --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi >>>> +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi >>>> @@ -6,6 +6,7 @@ >>>> */ >>>> #include <dt-bindings/clock/qcom,gcc-sdm845.h> >>>> +#include <dt-bindings/clock/qcom,gpucc-sdm845.h> >>>> #include <dt-bindings/clock/qcom,rpmh.h> >>>> #include <dt-bindings/interrupt-controller/arm-gic.h> >>>> #include <dt-bindings/soc/qcom,rpmh-rsc.h> >>>> @@ -989,6 +990,28 @@ >>>> cell-index = <0>; >>>> }; >>>> + gpu_smmu: iommu at 5040000 { >>>> + compatible = "qcom,sdm845-smmu-v2", >>>> "qcom,smmu-v2"; >>> >>> Which of "sdm845" or "msm8996"[1] is the actual SoC name here? >> Well, the bindings use the SoC prefix with smmu-v2, so it should be >> sdm845 for this SoC. This is same as I posted in my v1 of the series [2]. >> Using 8996 based string in sdm845 makes things look awful. > You need to list valid values of '<soc>' in the binding. Otherwise we > get this confusion. Sorry for delayed response, I was away on vacation. I will list down the valid values for '<soc>' as suggested, and respin this series, and smmu bindings patch that comes as part of the runtime pm series [1]. [1] https://lore.kernel.org/patchwork/patch/968017/ Best regards Vivek > > Rob ^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v2 3/3] dts: arm64/sdm845: Add node for qcom,smmu-v2 2018-08-27 8:56 ` Vivek Gautam @ 2018-08-27 11:12 ` Vivek Gautam 0 siblings, 0 replies; 9+ messages in thread From: Vivek Gautam @ 2018-08-27 11:12 UTC (permalink / raw) To: linux-arm-kernel On 8/27/2018 2:26 PM, Vivek Gautam wrote: > Hi Rob, Robin, > > > On 8/15/2018 4:27 AM, Rob Herring wrote: >> On Wed, Aug 15, 2018 at 01:09:43AM +0530, Vivek Gautam wrote: >>> Adding Jordan here. >>> >>> On Tue, Aug 14, 2018 at 4:19 PM, Robin Murphy <robin.murphy@arm.com> >>> wrote: >>>> Hi Vivek, >>>> >>>> On 14/08/18 11:27, Vivek Gautam wrote: >>>>> Add device node for qcom,smmu-v2 available on sdm845. >>>>> This smmu is available only to GPU device. >>>>> >>>>> Signed-off-by: Vivek Gautam <vivek.gautam@codeaurora.org> >>>>> --- >>>>> ?? arch/arm64/boot/dts/qcom/sdm845.dtsi | 23 +++++++++++++++++++++++ >>>>> ?? 1 file changed, 23 insertions(+) >>>>> >>>>> diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi >>>>> b/arch/arm64/boot/dts/qcom/sdm845.dtsi >>>>> index 1c2be2082f33..bd1ec5fa5146 100644 >>>>> --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi >>>>> +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi >>>>> @@ -6,6 +6,7 @@ >>>>> ??? */ >>>>> ???? #include <dt-bindings/clock/qcom,gcc-sdm845.h> >>>>> +#include <dt-bindings/clock/qcom,gpucc-sdm845.h> >>>>> ?? #include <dt-bindings/clock/qcom,rpmh.h> >>>>> ?? #include <dt-bindings/interrupt-controller/arm-gic.h> >>>>> ?? #include <dt-bindings/soc/qcom,rpmh-rsc.h> >>>>> @@ -989,6 +990,28 @@ >>>>> ???????????????????????? cell-index = <0>; >>>>> ???????????????? }; >>>>> ?? +???????????? gpu_smmu: iommu at 5040000 { >>>>> +?????????????????????? compatible = "qcom,sdm845-smmu-v2", >>>>> "qcom,smmu-v2"; >>>> >>>> Which of "sdm845" or "msm8996"[1] is the actual SoC name here? >>> Well, the bindings use the SoC prefix with smmu-v2, so it should be >>> sdm845 for this SoC. This is same as I posted in my v1 of the series >>> [2]. >>> Using 8996 based string in sdm845 makes things look awful. >> You need to list valid values of '<soc>' in the binding. Otherwise we >> get this confusion. > > Sorry for delayed response, I was away on vacation. > I will list down the valid values for '<soc>' as suggested, and respin > this series, and > smmu bindings patch that comes as part of the runtime pm series [3]. > > [3] https://lore.kernel.org/patchwork/patch/968017/ > I have updated the binding doc with valid values for '<soc>' string [4]. Kindly review this based on [4]. [4] https://lore.kernel.org/patchwork/patch/977888/ Best regards Vivek ^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2018-08-27 11:12 UTC | newest] Thread overview: 9+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2018-08-14 10:27 [PATCH v2 0/3] Enable smmu support on sdm845 Vivek Gautam 2018-08-14 10:27 ` [PATCH v2 1/3] dt-bindings: arm-smmu: Add binding doc for Qcom smmu-500 Vivek Gautam 2018-08-14 10:27 ` [PATCH v2 2/3] dts: arm64/sdm845: Add node for arm,mmu-500 Vivek Gautam 2018-08-14 10:27 ` [PATCH v2 3/3] dts: arm64/sdm845: Add node for qcom,smmu-v2 Vivek Gautam 2018-08-14 10:49 ` Robin Murphy 2018-08-14 19:39 ` Vivek Gautam 2018-08-14 22:57 ` Rob Herring 2018-08-27 8:56 ` Vivek Gautam 2018-08-27 11:12 ` Vivek Gautam
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